First, Professor Asenov doesn’t address the floating body (Kink effect) and self-heating effects that are intrinsic to the FinFETs on SOI. Second, please see the three different fin shapes as shown in Fin 1, Fin 2 and Fin 3. Their shapes are quite different even seen by naked eyes. Despite such differences the on-current, I-ON is not significantly different or only within 4 percent range according to Prof. Asenov. This is indeed negligibly small compared with process variation across the chip or across the wafer. How this can be? Such small difference in the I-ON may be due to the differences in the volume inversion for the different fin shapes. Each fin has different volume inversion at the upper part and full depletion at the lower part because of the trapezoidal fin shape. The volume inversion contributes higher I-ON than the fully depleted case. The narrowest at the top fin (Fin 3) has the largest volume inversion, Fin 1 is next, and Fin 2 is the least or may be no volume inversion. As a result, the I-ON of each fin ends up in being almost equal, although significant differences in the shapes of three fins. It shows the fin shape is not a big concern for FinFETs on BULK. S. kim
No disrespect, but; I am always amazed how arrogantly Intel outsiders always "believe" they know better; when, as Chipguy1 correctly noted, "Intel is a ... data driven company" and the_floating_ gate posted M. Bohr's "one on one" discussion of balanced mix of concerns and factors that Intel weights when choosing a technology.
I guess we will see who has the last word
"Finfets need to be on SOI". I think both you and he will be proven right."
Man. I agree with GSS. I am designer now with past process training. We dont bin our parts so this variation woulld be a big issues. Do I really want to make each transistor on a random plane versus standard 100 surface?
At least if fin was vertical I would have consistent 110 plane. When I look at the 3 fins it's a crap shoot what plane of silicon transistor is fabricated on.
For the first time, at the 2012 Symposium on VLSI Technology (June 12 - 15), Intel will be reporting technical details of its state-of-the-art
Tri-gate 22-nm CMOS technology on bulk silicon which has entered volume production.
Program information about the two VLSI Symposia can be viewed here (Technology): http://www.vlsisymposium.org/technology/technical.html
and (Circuits): http://www.vlsisymposium.org/circuits/technical.html
While Intel has undoubtedly developed it's own proprietary approach to deal with the channel height definition and short channel leakage problems alluded to by Professor Asenov regarding
"bulk" devices, these problems were actually anticipated some time ago by HiperSem through the incorporation of a dual-polarity source/drain
The use of a dual-polarity source/drain device
architecture solves a number of problems and creates additional opportunities simultaneously by defining the active channel height according to the "depth" of the source drain junction, as opposed to the height of the "fin" itself.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.