I agree with the SOI conclusion. I think if you look at leakage and include gate oxide thickness variation and fin height variation your conclusion is even stronger.
The gate oxide thickness at the botton of the fin includes both the dark and light yellow in the figure above. At the bottom of the fin is a very poorly controlled device with a thick fin and thick gate oxide. This bulk finfet with sloped fins must have very high bottom fin leakage and intel will need to fix this for its mobile cell phone and tablet finfet process to be competitive (likly why intel's mobile finfets are still a year away and foundries have more advanced process technology in mobile market today (foundry 28nm vs intel 32 for intel atom line).
Prof. Fossum has published technical papers on this issue and concluded the same. "Finfets need to be on SOI". I think both you and he will be proven right.
Lastly, I know Intel is buying good quantity of SOI wafers so I think Intel is for certain investigating SOI as a fix to its problems.
For a very concise summary by Prof. Fossum (an industry giant; at U. FLA) on why FinFETs should be on SOI, see his short piece in ASN from 2007 (http://www.advancedsubstratenews.com/2007/05/a-perspective-on-multi-gate-mosfets/), where he concludes: "Most importantly, the underlying BOX effectively suppresses the source-drain leakage current under the gated fin-body (see the figure). Bulk Si would require heavy doping to suppress this current, as well as to effect reasonable device isolation. But one of our goals with MuGFETs is to get away from doping and the random effects it causes: the only pragmatic way to do that is to put the UTB* FinFET on SOI." (*UTB=ultrathin body; MuGFET=multigate FET, such as FinFET, trigate, etc.)
Thanks. I think intel is a 100% data driven company except on the issue of SOI. My contact at intel claims topic of SOI is more like a religion. Intel has alway been a "non SOI believer" .
Intel's CPUs run very high leakage (in range of 25W for desktop) so I also guess subfin leakage was not an issue for their CPU products. This leakage issue only surfaced when they tried to adopt bulk finfet for mobile.
the fact that at 22-nm Intel's FinFETs are trapezoidal rather than rectangular in cross-section (see Intel's FinFETs are less fin and more triangle).
Plasma etch challenges for FinFET transistors
check the cross section...
(1) figure shows STI depth is deeper for the outer fins so there is etch loading that will make outer fin different than inner fin. Since fins are formed by spacers ... Proximity correction is not really possible.
(2) all this variation might still be ok for a CPU where wide bins are sold and many fins are used for a transistor but for GPU it appears transistors would mostly use 1 or 2 fins so without many fin averaging I would expect transistor to transistor variation to be much worse for a GPU versus CPU ... and analog circuits too would have degraded matching unless planar devices are fabricated on same chip as finfet.
(3) there must also be a lot of fin height variation. From fin figure it is even hard to clearly define fin height since oxide beaks so much at the bottom of the fin
(4) even the work function thickness varries in the figure and I have see papers where metal grain would varry depending on fin side wall slope so that is another source of threshold variation
My guess is you will need ideal rectangular fins and SOI for this to be robust in manufacturing?
1.)I already posted M. Bohr's "one on one" where he addressed SOI vs Bulk - it's not that Intel did not look at SOI - according to him they did but found that bulk is a little more cost effective.
Bohr even stated that he expects TriGate to emerge based on SOI in the future.
I am not device guru but SOI has "preimplanted"
of dopants and this thin layer of dopants might result in "notching" during the etch.
I am just guessing
2.) Extendability was and is always Key for Intel - IOW current process must be extended over several generations
3.) I don't see why Intel can not work with testwafers @ 14nm and 10 nm - the litho roadmap is defined at least all the way to 10nm
4.) Yield depends on many factors - we don't really what kind of interactions are present
5.) Process window is also key parameter for Intel - but that's nothing new.
The "Motherfab" develops a process and than transfers it to other fabs
Yes, thank you for links. Agreed intel has large database on SOI. I think the question the industry is trying to answer is for the mobile market does it follow intel or use SOI. Does even intel move to SOI for mobile chips at 22nm or at 14nm to fix the issues uncovered by GSS and Chipworks. GSS thinks answer needs to be yes.
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