I agree with the SOI conclusion. I think if you look at leakage and include gate oxide thickness variation and fin height variation your conclusion is even stronger.
The gate oxide thickness at the botton of the fin includes both the dark and light yellow in the figure above. At the bottom of the fin is a very poorly controlled device with a thick fin and thick gate oxide. This bulk finfet with sloped fins must have very high bottom fin leakage and intel will need to fix this for its mobile cell phone and tablet finfet process to be competitive (likly why intel's mobile finfets are still a year away and foundries have more advanced process technology in mobile market today (foundry 28nm vs intel 32 for intel atom line).
Prof. Fossum has published technical papers on this issue and concluded the same. "Finfets need to be on SOI". I think both you and he will be proven right.
Lastly, I know Intel is buying good quantity of SOI wafers so I think Intel is for certain investigating SOI as a fix to its problems.
For a very concise summary by Prof. Fossum (an industry giant; at U. FLA) on why FinFETs should be on SOI, see his short piece in ASN from 2007 (http://www.advancedsubstratenews.com/2007/05/a-perspective-on-multi-gate-mosfets/), where he concludes: "Most importantly, the underlying BOX effectively suppresses the source-drain leakage current under the gated fin-body (see the figure). Bulk Si would require heavy doping to suppress this current, as well as to effect reasonable device isolation. But one of our goals with MuGFETs is to get away from doping and the random effects it causes: the only pragmatic way to do that is to put the UTB* FinFET on SOI." (*UTB=ultrathin body; MuGFET=multigate FET, such as FinFET, trigate, etc.)
Thanks. I think intel is a 100% data driven company except on the issue of SOI. My contact at intel claims topic of SOI is more like a religion. Intel has alway been a "non SOI believer" .
Intel's CPUs run very high leakage (in range of 25W for desktop) so I also guess subfin leakage was not an issue for their CPU products. This leakage issue only surfaced when they tried to adopt bulk finfet for mobile.
No disrespect, but; I am always amazed how arrogantly Intel outsiders always "believe" they know better; when, as Chipguy1 correctly noted, "Intel is a ... data driven company" and the_floating_ gate posted M. Bohr's "one on one" discussion of balanced mix of concerns and factors that Intel weights when choosing a technology.
I guess we will see who has the last word
"Finfets need to be on SOI". I think both you and he will be proven right."
the fact that at 22-nm Intel's FinFETs are trapezoidal rather than rectangular in cross-section (see Intel's FinFETs are less fin and more triangle).
Plasma etch challenges for FinFET transistors
check the cross section...
(1) figure shows STI depth is deeper for the outer fins so there is etch loading that will make outer fin different than inner fin. Since fins are formed by spacers ... Proximity correction is not really possible.
(2) all this variation might still be ok for a CPU where wide bins are sold and many fins are used for a transistor but for GPU it appears transistors would mostly use 1 or 2 fins so without many fin averaging I would expect transistor to transistor variation to be much worse for a GPU versus CPU ... and analog circuits too would have degraded matching unless planar devices are fabricated on same chip as finfet.
(3) there must also be a lot of fin height variation. From fin figure it is even hard to clearly define fin height since oxide beaks so much at the bottom of the fin
(4) even the work function thickness varries in the figure and I have see papers where metal grain would varry depending on fin side wall slope so that is another source of threshold variation
My guess is you will need ideal rectangular fins and SOI for this to be robust in manufacturing?
1.)I already posted M. Bohr's "one on one" where he addressed SOI vs Bulk - it's not that Intel did not look at SOI - according to him they did but found that bulk is a little more cost effective.
Bohr even stated that he expects TriGate to emerge based on SOI in the future.
I am not device guru but SOI has "preimplanted"
of dopants and this thin layer of dopants might result in "notching" during the etch.
I am just guessing
2.) Extendability was and is always Key for Intel - IOW current process must be extended over several generations
3.) I don't see why Intel can not work with testwafers @ 14nm and 10 nm - the litho roadmap is defined at least all the way to 10nm
4.) Yield depends on many factors - we don't really what kind of interactions are present
5.) Process window is also key parameter for Intel - but that's nothing new.
The "Motherfab" develops a process and than transfers it to other fabs
Yes, thank you for links. Agreed intel has large database on SOI. I think the question the industry is trying to answer is for the mobile market does it follow intel or use SOI. Does even intel move to SOI for mobile chips at 22nm or at 14nm to fix the issues uncovered by GSS and Chipworks. GSS thinks answer needs to be yes.
While Intel has undoubtedly developed it's own proprietary approach to deal with the channel height definition and short channel leakage problems alluded to by Professor Asenov regarding
"bulk" devices, these problems were actually anticipated some time ago by HiperSem through the incorporation of a dual-polarity source/drain
The use of a dual-polarity source/drain device
architecture solves a number of problems and creates additional opportunities simultaneously by defining the active channel height according to the "depth" of the source drain junction, as opposed to the height of the "fin" itself.
For the first time, at the 2012 Symposium on VLSI Technology (June 12 - 15), Intel will be reporting technical details of its state-of-the-art
Tri-gate 22-nm CMOS technology on bulk silicon which has entered volume production.
Program information about the two VLSI Symposia can be viewed here (Technology): http://www.vlsisymposium.org/technology/technical.html
and (Circuits): http://www.vlsisymposium.org/circuits/technical.html
Man. I agree with GSS. I am designer now with past process training. We dont bin our parts so this variation woulld be a big issues. Do I really want to make each transistor on a random plane versus standard 100 surface?
At least if fin was vertical I would have consistent 110 plane. When I look at the 3 fins it's a crap shoot what plane of silicon transistor is fabricated on.
First, Professor Asenov doesn’t address the floating body (Kink effect) and self-heating effects that are intrinsic to the FinFETs on SOI. Second, please see the three different fin shapes as shown in Fin 1, Fin 2 and Fin 3. Their shapes are quite different even seen by naked eyes. Despite such differences the on-current, I-ON is not significantly different or only within 4 percent range according to Prof. Asenov. This is indeed negligibly small compared with process variation across the chip or across the wafer. How this can be? Such small difference in the I-ON may be due to the differences in the volume inversion for the different fin shapes. Each fin has different volume inversion at the upper part and full depletion at the lower part because of the trapezoidal fin shape. The volume inversion contributes higher I-ON than the fully depleted case. The narrowest at the top fin (Fin 3) has the largest volume inversion, Fin 1 is next, and Fin 2 is the least or may be no volume inversion. As a result, the I-ON of each fin ends up in being almost equal, although significant differences in the shapes of three fins. It shows the fin shape is not a big concern for FinFETs on BULK. S. kim
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