Thanks Frank as always for your insight. This is a very succinct explanation of the barriers to the Holy Grail of plug and play IP reuse. It seems like one of those things that sounds so good in theory, yet in practice is much more complicated.
It has been the dream for a long time, and no I don't think we are close to realizing it.
This relates directly to the concept of IP re-use. There are indeed some digital IP blocks that can be and are re-used exactly as-is, no changes, with straight-forward implementation, timing closure and functional verification suites.
The problems arise when "re-use" becomes "re-use with some changes". The changes don't necessarily even have to be inside the IP block, but rather in the surrounding environment (i.e., the other IP blocks to which it connects).
When you assess the affect of the changes, no matter how small, now you've got real engineering work to do, and all bets are off, despite the pedigree of the IP and its history of successful use on other chips.
In my experience, most IP re-use falls in the category of "re-use with changes." Sometimes the impact of the changes is so substantial that you end up starting over, perhaps even at the architecture level.
Who remembers the Virtual Component Exchange (VCX)?
In 1998 "Foundation laid for IP clearinghouse"
In 2004 "System-level Beach acquires Scots IP portal company" http://www.eetimes.com/electronics-news/4123244/System-level-Beach-acquires-Scots-IP-portal-company
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...