Embedded Systems Conference
Breaking News
Newest First | Oldest First | Threaded View
User Rank
re: TI details TSV integration in 28-nm CMOS
docdivakar   6/23/2012 12:42:03 AM
In the paragraph "Three-dimensional chips using TSVs—which connect levels of die to each other—have been in development..." I believe the author is making a comment on what is in production under the broad definition of 3D IC's (monolithic vs. stacked). Trigate by Intel is one implementation of monolithic which has many variants, some of which have been presented here before. I understand the paragraph may be slightly confusing when made in an article which is addressing 3D IC using TSV's but it is a passing comment made to relate the reader to the general context of 3D ICs. TI is one of the many to have "mastered" TSV technology at 28nm. We already know of Samsung and Micron announcing memory products made using TSV's. Some of the numbers cited in the article are specific to the TSV diameter and aspect ratio. I believe the 4um distance at which the effects of TSV's diminished was for a TSV of 10x60um. The trick is in post-TSV plating annealing and the corresponding residual stress containment that determines the keepout rules. More details on the paper by TI can be found here: http://www.vlsisymposium.org/technology/tec_pdf/12-T-ap-web.pdf TI's abstract can be found in p. 15. I disagree with TI person's statement "...most of the systematic issues in the wafer processing and packaging side are mostly behind us.." in a general context. The design rules for keepouts as well as TSV dia and aspect ratios are evolving and are application dependent. There may be few players with well-known TSV unit cell design guidelines but we have a long way to go before incorporating these into EDA tools. MP Divakar

User Rank
re: TI details TSV integration in 28-nm CMOS
Denis.Giri   6/18/2012 7:19:08 AM
The author of this article must have had too much to drink before he wrote this. Intel FinFet/tri-gate/22nm3D transistors have nothing to do with TSV technology and 3D integration (in the package) Intel made transistors that go slightly away from the "planar" technology we've been using since the 50's. TI has "mastered" Through-Silicon-Vias in order to make System-in-Packages where you stack several chips on top of each other in order to make a 3D SiP. It's not the only way to make 3D SiP, but it's probably the best, and it opens the way for "WideIO" memories. Intel made improvements at the transistor level. TI on the package level. Not the same thing.

User Rank
re: TI details TSV integration in 28-nm CMOS
goafrit   6/15/2012 9:22:29 AM
-Three-dimensional chips using TSVs—which connect levels of die to each other—have been in development for years. Intel Corp. is currently in production of its 22-nm 3-D chips, which use a technology that the company refers to as tri-gate transistors. - Intel has this as a product. What is new here for TI?

User Rank
re: TI details TSV integration in 28-nm CMOS
chipchap42   6/14/2012 7:50:24 PM
Dylan, Trigate has nothing to do with this kind of 3D - the transistors themselves are 3D in structure but monolithic in terms of the silicon. This kind of 3D refers to joining different bits of silicon together using TSVs.

User Rank
re: TI details TSV integration in 28-nm CMOS
Kuenyu   6/14/2012 6:44:13 PM

As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Like Us on Facebook
Special Video Section
The LTC®6363 is a low power, low noise, fully differential ...
Vincent Ching, applications engineer at Avago Technologies, ...
The LT®6375 is a unity-gain difference amplifier which ...
The LTC®4015 is a complete synchronous buck controller/ ...
The LTC®2983 measures a wide variety of temperature sensors ...
The LTC®3886 is a dual PolyPhase DC/DC synchronous ...
The LTC®2348-18 is an 18-bit, low noise 8-channel ...
The LT®3042 is a high performance low dropout linear ...
Chwan-Jye Foo (C.J Foo), product marketing manager for ...
The LT®3752/LT3752-1 are current mode PWM controllers ...
LED lighting is an important feature in today’s and future ...
Active balancing of series connected battery stacks exists ...
After a four-year absence, Infineon returns to Mobile World ...
A laptop’s 65-watt adapter can be made 6 times smaller and ...
An industry network should have device and data security at ...
The LTC2975 is a four-channel PMBus Power System Manager ...
In this video, a new high speed CMOS output comparator ...
The LT8640 is a 42V, 5A synchronous step-down regulator ...
The LTC2000 high-speed DAC has low noise and excellent ...
How do you protect the load and ensure output continues to ...