Trigate has nothing to do with this kind of 3D - the transistors themselves are 3D in structure but monolithic in terms of the silicon. This kind of 3D refers to joining different bits of silicon together using TSVs.
-Three-dimensional chips using TSVs—which connect levels of die to each other—have been in development for years. Intel Corp. is currently in production of its 22-nm 3-D chips, which use a technology that the company refers to as tri-gate transistors. -
Intel has this as a product. What is new here for TI?
The author of this article must have had too much to drink before he wrote this. Intel FinFet/tri-gate/22nm3D transistors have nothing to do with TSV technology and 3D integration (in the package)
Intel made transistors that go slightly away from the "planar" technology we've been using since the 50's.
TI has "mastered" Through-Silicon-Vias in order to make System-in-Packages where you stack several chips on top of each other in order to make a 3D SiP. It's not the only way to make 3D SiP, but it's probably the best, and it opens the way for "WideIO" memories.
Intel made improvements at the transistor level. TI on the package level. Not the same thing.
In the paragraph "Three-dimensional chips using TSVs—which connect levels of die to each other—have been in development..." I believe the author is making a comment on what is in production under the broad definition of 3D IC's (monolithic vs. stacked). Trigate by Intel is one implementation of monolithic which has many variants, some of which have been presented here before. I understand the paragraph may be slightly confusing when made in an article which is addressing 3D IC using TSV's but it is a passing comment made to relate the reader to the general context of 3D ICs.
TI is one of the many to have "mastered" TSV technology at 28nm. We already know of Samsung and Micron announcing memory products made using TSV's.
Some of the numbers cited in the article are specific to the TSV diameter and aspect ratio. I believe the 4um distance at which the effects of TSV's diminished was for a TSV of 10x60um. The trick is in post-TSV plating annealing and the corresponding residual stress containment that determines the keepout rules.
More details on the paper by TI can be found here:
TI's abstract can be found in p. 15.
I disagree with TI person's statement "...most of the systematic issues in the wafer processing and packaging side are mostly behind us.." in a general context. The design rules for keepouts as well as TSV dia and aspect ratios are evolving and are application dependent. There may be few players with well-known TSV unit cell design guidelines but we have a long way to go before incorporating these into EDA tools.