A5X uses 45nm "LP" flavor. For LP foundry Samsung,TSMC,UMC do not use SiGe for pFET strain. See
Regarding high k gates, foundry did not adopt at 45nm. Foundry adopted high k at 32nm and most versions of 28nm (except 28LP)
Historically smaller = lower power. But even at 20nm the early foundry models don't show much power reduction from 28nm. I too am not sure how the roadmap plays out. I think we have been spoiled in the past with advanced nodes offering lower power, lower cost, and increased performance.
Just as Professors Fossum and Assanov have published on bottom fin leakage in bulk finFETs, Professor Bokor of Berkeley has published nearly a decade ago on the electrical variation (see "Sensitivity of Double-Gate and FinFET Devices to Process Variations"). Dr. Bokor's conclusions for 20nm finFETs are interesting: To control variability, 1nm fin with control (3 sigma), no fin dopants, and 1-2A gate oxide thickness is required. Can industry achieve these kinds of targets?
Some quotes from his paper are along the lines of discussed in the VLSI article.
"The high sensitivity of leakage current to body thickness variation may limit the application of the devices in low power ICs."
"The variation caused by random dopant placement in the channel region might make it impossible to meet tight circuit specifications required for manufacturing."
"In general, the fabrication process of double-gate MOSFET devices (e.g., FinFET) is more complicated than that of single gate devices, which will potentially bring more nonuniformity during fabrication. For example, in FinFET devices, the gate oxide is on the etched sidewall of the fin, and its uniformity is more difficult to control. The channel-oxide interface condition is determined by the sidewall roughness of the fin."
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