I think your right for market at large but I wounder if Samsung is close with this technology. They have been working on TSS for DRAM and FLASH. Might give them and apple a big performance and power advantage in app SOCs? Might be another area apple goes deep into supple chain like the did with mining special Al.
Borkor also nailed perhaps the biggest issue with sloped fins: oxide thickness variation.
Another quote form his journal paper.
"Unlike the planar MOSFET devices, the gate dielectric of FinFET devices is vertical. Its thickness and the Si/SiO inter- face are affected by sidewall SLOPE and roughness of the fin. We may expect some difficulties to get the same uniformity as the planar case."
In the Chipworks pictures, the gate oxide thickness does vary a lot fin to fin and even more within a fin. Much much more than Borkors 1-2A requirement. 10X more?
I continue to think design issues caused by transistor variation are not appreciated. . Author and even Borkor's paper did not talk about systematic variation with FinFETs but I just continue to be surprised by the outer to inner fin variation as seen in differences in the STI depth (see outer to inner fins STI depth). If I understand how this works most of my design would use between 1, 2 or at most 3 fins per transistor. Fin width being difference for 1,2 or 3 fin devices and Borkor's suggest this needs to be controlled within 1nm (=10 angstroms = 2 Si lattice constants?).
FDSOI has some advantages and disadvantages. The concept has been worked on in the industry for 15 years.
The biggest advantages are low leakage and low transistor variability.
The biggest disadvantages are lower pFET drive current (lower performance) since eSiGe is much less effective in mobility enhancement via strain and an easy method to adjust threshold voltage (SOCs require a wide dynamic range in Ion/Ioff which is achieved by threshold voltage).
I think your spot on. When I look at the product power reduction with 3D fins on 22nm Ivy bridge, it does not seem much if any improvement over a standard process shrink? Even if i use Intel numbers perhaps is an effective "2.2D" . Putting on my system architect hat, I think much larger power savings (as compared to 3D fins effective 2.2D) are possible with 3D Through Si via Stacking (TSS) between the DRAM and apps processor. I also think 28nm is the right node to introduce TSS as well.
Any process experts on TSS care to comment?
What makes 14 nm difficult could be the move to 3d fin transistor, that seems much more drastic than more pattern decomposition. And how about TSVs, for real 3D not 2.5, wouldn't it be easier to introduce at 28 nm rather than 14 nm?
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