This old EETimes article describes the history of how Intel roped ASML into EUV back in 1999.
The cowboy tech company on hormones that was Intel needed a NGL tech to prevent being dominated by IBM, Siemens and others who were focused on e-beam, ion beam and X-rays. EUV was already ruled out by the others for the issues which continue to plague it today (source, multilayer defects, etc.). But Intel needed to grab an NGL weapon to enter the debate.
Thirteen years later, Intel now realizes that NGL was not needed after all, it can already afford quadruple patterning. It needs to fulfill a moral obligation to ASML, this deal appears the best way.
The big impact is ~$3B for 15% of ASML. That's a big charge. 0.7B for 450 mm and 0.3B for EUV means 450 mm more important now. How can anyone say a technology with long unresolved issues will be cheaper, beats me.
Intel plans to move double patterning at 14nm into production in 2013 and also expects to initiate an EUV pilot line (initially using Intel 3100 tool) at the same time. At 10nm, Intel likely will use complimentary patterning (i.e. mix and match of EUV and QP/ArF immersion techniques). With Intel moving to high-volume 14nm production in 2013 and critical layers using ArF Dry and immersion tools set to double from 23 to 46, Barclays anticipates a meaningful step up in wafer-fab equipment (WFE) spend from Intel in 2013, particularly for litho – look for order pickup late 2012.
Wasn't ASML dragging its feet on starting 450-mm development? A lot of people I think expected that tool makers would make Intel and other chip makers foot part of the bill for 450-mm development after they all got burned at 300-mm.
I hear it's because ASML did not want to do both EUV and 450mm. Too costly. Not clear what the next level of detail is.
(1)does this mean ASML is now going to develop 193i 450mm steppers.
(2) stop development of 300mm EUV steppers that were sold for more than 100€.
(3) then deveop 450mm EUV
I think intel is seeing same problem as foundry. Double patterning and even triple patterning is possible/doable. However, wafer cost increases and cost per transistor does not decrease (so slow down or stopping of Moores law !). Foundry seeing this at 20nm and severe at 14nm. Intel being behind for back end metal wiring design rules now sees this at 14/10nm.
So intel needs to write a $4B check. On top of increasing R/D cost.
This is what slow down in Moore's law looks like. The economic advantage of keeping making things smaller diminishes. ...advanced node delivers less but cost more to develop.
Dylan.... I disagree with Gartner. 450mm is a solved problem technically. it just needs money and Equipment Vendor buy-in. That will not take til 2019 or 2020. On the other hand EUV is still a technical challenge. Intel has mastered double patterning. If push comes to shove they will go to quadruple patterning and get to 10nm and beyond. However that is expensive and hence they are pushing very hard for 450mm to take advantage of the cost curve primarily.
EUV is still a long term challenge and my guess is it will not be ready till atleast 7nm node.
Any of the insiders care to comment??
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.