Industry talk of EUV, 450mm, 3D finfets does not seem to be based in reality. At what cost?
Our company is still making most of our chips on 40/45 since die cost us more on 28nm due to high wafer prices, restrictive design rules, and lower 28 vs 40/45 defect and parametric yield.
It's about time industry fess up on true status of EUV. TSMC has state EUV required for a cost viable 14nm.
" Imec has been running an ASML NXE:3100 for a year now, and its higher throughput means that process development is much easier compared to the days of the old alpha demo tool (ADT). Still, “higher throughput” is a relative term. The most wafers that Imec has run through their 3100 continuously is one lot – 23 wafers – taking about five hours. Thirteen minutes per wafer is a big improvement over several hours per wafer, but still far from adequate."
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...