Industry talk of EUV, 450mm, 3D finfets does not seem to be based in reality. At what cost?
Our company is still making most of our chips on 40/45 since die cost us more on 28nm due to high wafer prices, restrictive design rules, and lower 28 vs 40/45 defect and parametric yield.
It's about time industry fess up on true status of EUV. TSMC has state EUV required for a cost viable 14nm.
" Imec has been running an ASML NXE:3100 for a year now, and its higher throughput means that process development is much easier compared to the days of the old alpha demo tool (ADT). Still, “higher throughput” is a relative term. The most wafers that Imec has run through their 3100 continuously is one lot – 23 wafers – taking about five hours. Thirteen minutes per wafer is a big improvement over several hours per wafer, but still far from adequate."
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.