Your comment "so the chip assembly is repeated over and over as pieces are completed or updated" reminds me of my boss's mantra -- "build it early and build it often." We've been doing it that way for almost 20 years.
Considering the tight schedules a chip development usually faces, I think most chip designs follow what you described as Just In Time chip development. Why? Simply because there is never time to develop blocks first and the chip later, and nobody wants surprises at the end -- surprises mean delays.
The final chip assembly and verification processes should be the MOST predictable part of the schedule, because the team has done this several times during the course of the development, and the final iteration that leads to tapeout is just one more turn of the crank.
Blog Doing Math in FPGAs Tom Burke 15 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...