Reading between the lines on this one it looks lik there is going to a hiatus in Moore's Law while Intel, ASML and others reapply themselves to this.
It also looks like the transition to 450-mm may be easier to implement than the one to EUV, which has got Intel thinking.
Moore's law is about doubling the number of transistors AND the new chip still costing the same (I.e. the cost per transistor goes down). What the industry is finding is Moore's Law is breaking down due to lithography cost (tools used to print the chips way too expensive). Next generation EUV steppers cost ~$150M and can only process 10 wafers per hour versus expected 160.
Intel needs to move its business model off Moore's law. Intel is spending more and more on a new silicon technology that is delivering less and less.
Only ASML has the edge technologies in lithography. ASML is still investing a lot in human and finacial resources in EUV. If Intel, Samsung and TSMC want 450mm fab, they have to involve .... push ASML to do it.
450mm was already considered close to hell freezing over, and it's already ahead of EUV. This might be a sign of realization by the industry. And the earliest production date has slipped to 2014, another sign of realization.
Uncertainty cannot help lower cost. Delay is the greatest cost of all. It may be time to really look at other options. So what happened to these other options like DSA, imprint, maskless, etc.?
Intel must double-down on 450mm because growing millimeters of silicon diameter is cheaper and far more predictable than reducing electromagnetic wavelengths to X-ray range. Presumably, ASML can build a 450mm stage (other, much smaller companies are) with greater success than the SXPL machine they are trying to build. Meanwhile, they sell multiple profitable immersion tools for optical multi patterning.
I can smell the desperation of intel, while competitors is chasing closer from everywhere, there is only one direction, up. and there is only sky there and it don't have a wing...
they better invest in CERN as well, they could offer quark level tech for them.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.