@sprite0022: Great comment! In a tiny market like EUV litho tools, or DW Ebeam, a monopoly is appropriate. There are better uses for this kind of investment money. Kudo's to Nikon and Canon for dropping out of the advanced litho game for DSRL's!
I think that both TriGate and TSV's are 3-D technolgies. Back to the basics of Moore's law - reduction of the area of the transistor and the cells used for creating microelectornics devices will reduce the cost of the manufactring. There are side benfits of potential increase in speed and reduced energy per switching action that can be capture through this effort. Moore's law will end due to laws of physiscs ( how small can switching device get). As part of getting closer to the the physics limit - there is need for more vertical structures to provide the finctionality needed to reduce space. In the previous 15-20 years it was by adding metal layers; Then came incorporation of new materils into the stack that required more processing (layers = vertical additions). Now we are in Tri Gate and TSVs that again - allow to build "High Risers"in different ways ( condos's in the bottom floor, or simply put one strucutre on top of the other). However - we get to the point that the saving in silicon area in each new generation will be offset by the cost of additional processing. That is when Moore's law that we enjoyed it for the last 4 decades, stops- probably a bit before the absolute physical limitaion.
Once we get to 10-14 nm, multipatterning will be more established than wherever EUV is at. There should be no further revolutionary changes in the litho patterning.
If we're starting over on other than Si most likely some contact method like imprint or soft stamping lithography might be the new starting point, not optical projection.
Complementary litho is too expensive, maybe only intel could afford it. Pitch splitting combined with a second NGL exposure - slower, more expensive and more risky than either by itself.
LELE is more reasonable in near term.
It's also hard to wrap gate+oxide around a Si channel within 20 nm.
How can you make such wild statements with no facts?
Actually not just no facts, but actual nonsense.
No comapny can make billions in profit from selling a third of its output under cost unless subsidized by a government or "rich daddy"...Intel has neither:)
In fact I did publish a response taking responsibility for my error in the case of reporting on that TAITRA report. You can find it here.
The report by the Taiwan External Trade Development Council (TAITRA) quoted an anonymous source saying that TSMC's projected delivery of 3-D chips matches that of Intel, the world's biggest chip maker. Intel announced with great fanfare in May that it would begin high-volume production of 3-D chips using tri-gate transistors by the end of the year.
Did you ever correct this story ?
You never did -
and now you're commenting on ASML?
FYI Solid State has an excellent site:
Blog Doing Math in FPGAs Tom Burke 22 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...