As for the TSV study at IITC (Fig. 6 in the linked blog post) the point is that for 5um TSVs, the gain in 3D wirelength shorting over 2D is minimal (90nm 2D at 75um goes to maybe 74um 3D). But for a 0.1um TSV, the wire shortening is quite significant (90nm 2D at 75um goes to 45um 3D).
Another way to look at it: The power savings of a factor of 2 does not come just by area savings and the resultant shorter wires with mon 3D (footprint is actually 4X lower), but also by the minimization of the slow metallization scaling 'bandaid' we all have been using for so many scaling generations--the repeaters/buffers. As they get eliminated by the mon3D shorter wires, the transistors become closer and the horizontal wires between them shorter….a positive feedback. Try it out on the MonolithIC3D website: 3D and 2D free simulator.
As for heat removal from the second layer (‘top’ one farthest away from the heat sink), the heat removal is not dominated by ‘double-sided’ convection, but by intentional conduction (think satellites as an analog, but we have a heat sink advantage they don’t); and if done properly, taking advantage of the mon3D dense vertical connects for thermal as well as electrical conduction, a lot of heat generation from the second layer can be taken to the heat sink. As Zvi mentioned, the paper with Stanford has been submitted.
Thanks for the support. And in respect to Singularity, we should be able to bring it sooner thank to monolithic 3D as we presented in our blog titled "Monolithic 3D IC Could Increase Circuit Integration by 1,000x": http://www.monolithic3d.com/2/post/2011/12/monolithic-3d-ic-could-increase-circuit-integration-by-1000x.html
As the CTO of IBM once said, "... somewhere between 130 nm and 90 nm, we lost scaling." Until then, a shrink was 2D. Then, we had to start thinning the metal to avoid skyscraper shorts. This means that the relative resistance of the metal goes UP, rather than staying constant as in previous shrinks. Higher metal resistance means relatively lower speed and higher power. So, shrink a chip and it becomes cheaper (in Si area) but slower and hotter. And that is why we have no 4 GHz Pentiums to this day. The 3.5 GHz Pentium 4 in 2004 was as close as it got.
And now the other shoe is falling. We have pulled out all the stops, with copper, halfnium oxide, etc. so we cannot stave off slower and hotter much longer. Maybe graphene (unobtanium?) will somehow save us. Or not.
3D may help - or not, as comments above seem to indicate.
The Singularity may be delayed until further notice.
What your reference compares is 3d-monolithic versus the wire length for stacked dice using TSV. I wouldn't argue with that. Unfortunately you used this to answer a comment that almost certainly related to use of a single larger 2d die. The advantages of somewhat reduced power then follow the law that I described. And I can't find any evidence for 3d-mono having a double-sided heatsink advantage whichcever case you choose. (Of course, if the process characteristics are different for the different 3d mono active layers, the cost advantage is clear.)
The preamble suggest that this might not be the place for detailed answers (which we do have). So I will just point out that the most important market for electronics these days is the 'smart mobility'. In this market the main concern is reduction of overall power per function. And the power reduction is actually by factor of 2 as we detail in: http://www.monolithic3d.com/2/post/2012/05/the-future-is-the-interconnect-iitc.html.
As for the issue of removal of the generated power we have worked on it with a team at Stanford and recently the work was reported in a paper submitted to IEDM.
Dedicated proponents can be the worst enemies of the case they are promoting. Sometimes the problem is saying sceptics' proper reservations are irrelevant without providing evidence; sometimes it's merely overselling the technology.
Consider the claim for "shorter lines means much less power..." Halving the area per se at best reduces the line length by a factor of sqrt(2), so the power-per-area increases.
There are special cases where 3D will require a similar number of layers to the parent processes, but this should not be confused with a general advantage. So far as I understand, the "thinner layers" applies only to the silicon, which is definitely not an advantage, as the high thermal conductivity of the substrate in practice provides significant spreading of heat. Moreover, the diagrams as presented place the multi-planar (monolithic 3-D) silicon layers between the substrate and the metallisation; if correct, double-sided heat sinking will be no more straightforward for these 3D structires than it would for 2D structures.
One reason 20 nm seems so painful is they are still using 0.7 shrink even with double patterning.
It would make more sense to get close to ~0.5 shrink on the layers which really need DP. Almost like skipping a node to make up.
3D tight arrangement is superior to planar except for thermal, which is its fatal weakness.
Blog Doing Math in FPGAs Tom Burke 2 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...