dylan: Why wait? Didn't you see the DRAM in the chip? PCM was supposed to replace both DRAM and NOR - why do you now need to add DRAM in the MCP? Please enlighten us!
No commercial product is using Micron's "volume" product, and none will ever will. The reasons have been explained to you numerous times.
Oh, and by the way, after Ovonyx goes bankrupt this year, it will all become clear to you.
I am hoping that the mechanism in the U of Penn research is the same as something I read in a research paper quite a while ago. That paper proposed a matrix with most of the vertices fixed, but particular pieces of some of the unit cells come loose. Like a bunch of tiny gates being opened. I have a vague memory that Mr. Neale has observed a similar mechanism in a cell with a very small cross section. I know that there is research being done on doping the chalcogenide with Fe, but I suggest that Prof. Agrawal try their nano-wires doped with Tb and Er. (2 separate wires) That is from another paper I read that reported anomalous results from some rare earth doped chalcogenides.
The PCM needs to primary questions to be answered and solved, 1. The price of the memory and 2. The reliability of the product using PCM throughout the globe. If this goes well then I think one can take of risk of using it in the proven designs.
Very interesting to me too. I think Prof. Agrawal's group attributed the amorphization to dislocation bunching under "electric wind" which I interpret to mean electromigration. But I haven't read the article myself. Need to go somewhere to get access.
Mr Rbtbob-I can assure you there was some in- house editorial discussion. I am still working through their paper. On the the "potential" NV memory front I am more impressed with the nmRAM (atomically dispersed metal) work from the same University. I have done some scaling exercises on the nmRAM and it looks good. It offers a very low write current but does require a bi-directional matrix isolating device.
In answer to your specific question, my first concern was understanding how the sample was physically supported. I think you have to consider the possibility that the material being subjected to the short pulses was under strain the local pressure wave could induce nano-cracks that appear at the surface.
Chopping away at the crystal structure with very small multiple reset pulses has been part of the PCM reset technique since day one. have a look at the 100 level PCM work at Stanford. Look under PCM Brain with EEtimes search engine.
In that case resolving the actual temperature at the grain boundaries, melting or otherwise is not trivial.It is not clear why this disorder is seen at the surface other than the strain provides a "crack" propagation mechanism.
Finally does this disordered material have a glass transition temperature and the other properties of the disordered PCM material created by melting and quenching. There is a non-melting order transition at the glass transition temperature perhaps without melting.
More on this later perhaps.
Mr. Neale, What do you think about the U of Penn research announced in June: "Now we have shown that there is a way to achieve this transition without melting the material," Agarwal said. "We show that short electrical pulses of a few hundred nanosecond duration gradually induce disorder in the material until it amorphizes."
(I could not find the research covered here on EE Times)
Dylan: Did Micron tell you how many of these 90nm devices in "volume production" were actually shipped and sold? More importantly how many product design- in wins were achieved?
"Proof of PCM's potential" I think PCM potential has been there for fifty years-for PCM realization of potential is the name of the game, with PCM devices that are competitive in price, performance and reliability.
In a comment added to my piece published July 2010
a reader cited a quote from Samsung “…Memory for portable consumer devices today is at a major turning point as mobile applications increasingly require more diverse memory technology,” said Jun Dong-soo, an executive vice president at Samsung Electronics.
“The launch of our PRAM in an advanced MCP solution for the replacement of 40 nm-class and finer geometry NOR meets this need head-on,” he said...."
The results of that head-on collision may have some relevance to Micron as they proceed along what appears to be the same road. For the new PCM I assume and hope “availability” means the 1G-bit MCP is fully qualified and with an associated data sheet. The write/erase lifetime cited for this 1 G-bit 45nm MCP device is given as 100,000 cycles, whereas Micron’s prediction for w/e cycle lifetime at 45nm was 10E9 cycles. This was discussed in
All things being equal, it may be churlish to describe this is anything but PCM progress; representing a scaling holding point until, and if, the very difficult PCM scaling problems ever get solved. My view is unless Micron can in short order get a scaled 8G-bit PCM in the MCP or their Cube (or even a multi-chip based 8G-bit PCM) they will suffer the same fate as the Samsung MCP-PCM. So continuing the road analogy above we hope they have their seat belts on.
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