I do agree that is the other wild card industry is not honest about.
Even if all the technical EUV problems are solved, just as likly at 10nm designers may not be able use use metal system (resistance too high) or transistor electrical characteristics too poor to be usable.
I think it is very clear the economic advantage of scaling is diminishing fast.
In fact we already see that at 20nm today. It is not delievering much cost, performance or power improvement over 28nm.
14/10nm can be made but companies that produce chips at these nodes will likly be no better and perhaps worse off than producing chips at 20/28nm.
Peter, we will see.
I just don't see equipment industry supporting 300mm and 450mm at the same node 10nm? for what 4 customers.
1 customer intel on 450?
3 customers on 300?
2 on each?
There is just too much work getting 2 tool to production level quality (particles, process uniformity etc.). Supporting repairs on both tools, etc.
Market is too small to support this double cost (in my opinion)
I think if 450 happens, at say 10nm ..I bet equipment suppliers like ASML will only develop one type of tool for the 10nm node specs.
I don't see things quite the way you do.
300-mm EUV will last a lot longer than 2 years.
ASML will start on 300-mm for EUV and then as and when Intel wants it they will (supposedly) also supply EUV machines able to process 450-mm wafers.
But they will carry on with 300-mm EUV because not everyone will move over to 450-mm.
Intel will followed by TSMC and Samsung but others could go 450-mm later.
The 2014 to 2016 are low through and not economical. Even it ASML hits 2016 wafer throughput targets (and there is no track record)...
Not much after 2016 450mm is suppose to come in (per same source ASML)
So I don't get the roadmap. 300mm EUV production for 2016-2018 then 450mm.
No way the industry is going to adopt 300mm EUV for just 2 years. No ecomonic benefit (increases cost not lower it).
Please pin these guys down on what exactly is their credible roadmap they are pushing !
except that Intel is already having to think about double-dpouble (quadruple) exposure which ends up being very costly in terms of dwell time on the machine.
But ultimately you may be comparing double exposure EUV that is expensive and quadruple exposure that doesn't work.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.