I'm amazed that ASML can continue to miss scheduled milestones in EUV litho and have any credibility left. I understand that they are not directly responsible for the source problems, the resist issues, the whole EUV mask infrastructure, etc. But forgive me if I don't have much faith in this four year throughput projection. I know ASML believes that 70 wafers per hour is good enough for adoption for high volume manufacturing, but I question that assertion as well.
@any1- I hear you. At a certain point it gets to be like the little boy who cried wolf. But in defense of ASML and everyone involved, what they are attempting to do is really difficult.
Have the pushouts resulted in some tarnished credibility? Probably a little bit. But I don't believe ASML would continue to spend millions of dollars on development and offer new targets for production if they didn't believe they would get there eventually. And I don't think Intel would have opened up its wallet if it wasn't presented with convincing evidence.
On the 70 wafers per hour being good enough, you may be right about that. But from what I heard last year at BACUS, I think that at this point chip makers would be more than happy with that as a starting point. Note that Meurice is now saying 125 wafers per hour by 2016, and that will I am sure be workable.
All this said, I do agree that the jury is still out on EUV.
Yes EUV is difficult - no question. But we've been at this several years now. You would think that at some point the estimates of future progress would become more realistic. Maybe you would even err on the side of caution so you could actually meet a milestone, or heaven forbid even beat one. I like ASML, and I think they make some great products, but ASML has been much more successful at marketing EUV than actually delivering on the technology.
except that Intel is already having to think about double-dpouble (quadruple) exposure which ends up being very costly in terms of dwell time on the machine.
But ultimately you may be comparing double exposure EUV that is expensive and quadruple exposure that doesn't work.
The 2014 to 2016 are low through and not economical. Even it ASML hits 2016 wafer throughput targets (and there is no track record)...
Not much after 2016 450mm is suppose to come in (per same source ASML)
So I don't get the roadmap. 300mm EUV production for 2016-2018 then 450mm.
No way the industry is going to adopt 300mm EUV for just 2 years. No ecomonic benefit (increases cost not lower it).
Please pin these guys down on what exactly is their credible roadmap they are pushing !
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.