Can you look into this. For a given chip in 20nm
True 14nm: porting chip should result in 2x more chips per wafer.
True 1/2 node (14 + 20)/2=17nm should result in 1.5X increase in chips per wafer.
And ideal moores law wafer price should be constant
So what does tsmc 16nm deliever regarding moores law. That will tells us if the node name is fake or real and if it offers any value.
(cost) is all I care about. The performance numbers foundry quotes are never true. Foundry does not understand chip design and hence makes many wrong assumptions when benchmarking performance. Just one example being they just quote "median performance" and I need to sell entire distribution.
I am told production for this TSMC "finfet 20nm" is 2H2015.
TSMC is very confused to think I would port all my 2013 20nm planar IP to a "finfet 20nm" called "16nm" for higher chip cost for a very small performance incrase at constant power.
Perhaps intel is right, is foundry model broken?
TSMC plans to use EUV at 10nm.
But these names now mean nothing.
As I posted above tsmc "16nm" is really "20nm" if node name is suppose to represent transistor density (i.e moores law vs slick marketing)
It's interesting that ASMLs Meurice is quoted as saying you need EUV for 14 nm node. My impression is that Intel has already frozen their 14 nm ground rules and they are not planning to use EUV litho. Maybe the foundries (TSMC, Samsung, Global Foundries, etc.) will need EUV for 14 nm logic? This is possible, but if EUV takes too long to develop I'm betting they will find another way.
ASML has good insight since it sells the tools and knows node printing specs.
Good ASML is at least honest in node description: TSMC is calling the 20/22 finfet version "16nm"
I don't see this being interesting: no cost improvement and likly higher cost for 10-20% performance at same power (and that is not chip power just a few digital blocks that speed up...analog, mixed signal, and I/O power is worse). Chip power might at best be half the TSMC number 5-10%.
So TSMC thinks I will do all the work of porting a design to pay higher chip cost for 5-10% chip improvement?