I would expect Mr. East to put his company in the best possible light.
The rest of the story is:
1. Intel is making 22nm FinFET chips now for Win7 and (shipping in October) Win 8 notebooks. I suspect ARM SOC makers would LOVE to get into the couple hundred million notebooks that ship a year if they didn't have a crippled variant of Win 8 and non-FinFET processes to deal with.
2. Those Intel 22nm notebook CPUs also have memory controllers, copious cache, graphics including (I believe) video acceleration and PCIe interfaces. So what's the missing Intel IP?
Peter was right, the ARM camp is behind in process technology. Don't let Mr. East's snappy comebacks fool you.
SoCs have up to three different voltages with corresponding gate oxide thicknesses. I/O typically uses 0.18 um 3.3 V for example. The finfet cost and complexity has to be included with non-finfet portion for overall SoC process cost-effectiveness consideration.
Here is some more Intel leakage data. I understand there is confusion in media on this. Another data point on this is from Intel's 22nm product.
See Toms hardware comparing 3.5 Ghz parts idle power increase for 22nm
trigate compared to 32 planar : 71W vs 66W. Transistor leakage is a key component of idle power. see next quote in article as well. "Intel admits that it didn’t do much of anything to cut Ivy Bridge’s power consumption beyond its adoption of 22 nm lithography. It’s not surprising, then, that idle power use doesn’t really change compared to last generation."
So product shows ~ same leakage, ~same performance (3.5Ghz).
Explaining this unexpected result on leakage and performance could be
a great article.
Here is the data. Intel 22nm device specs were published at vlsi 2012. Leakage current is 1 to 100nA/um. Foundry for mobile 28nm SOC is 10pA/um to 10nA/um. Foundry mobile is 10X to 100X lower depending on device.
Intel will have a finfet soc in market in 2013. Since its not in market we don't know leakage. Intel will improve finfet and improve leakage but my guess it will match foundry leakage (not beat it)
Can you share your reference that intel is shipping lower leakage with finfet than Foundry and what leakage number you are using vs ( 1-100nA/um I ref.)
Intel does not have
I think you are mis-using the numbers here to get to 30x. It is always important to reference what is being compared against.
Intel 'tri-gate' FinFETs may well be superior to planar bulk CMOS, which is what most other companies are offering at present.
But Intel triangular FinFETs are a few percent inferior to rectangular FinFETs on bulk silicon
And rectangular FinFETs on bulk silicon are 2 to 3.5 times worse than FinFETs-on-SOI, according to GSS. As yet nobody is making FinFET-on-SOI although it may come.
So Intel FinFETs may be the best for leakage performance in the market at present but not quite as good as previously hoped because of triangular cross-section, which may have been adopted for manufacturing reasons.
Looks like your right.
Intel marketing is "good". They had us believing 10x lower leakage with trigate. Turns out 3x worse. So a factor of 30x marketing versus reality.
Let's see how they market the news when they switch to SOI.
I don't know exactly what Warren East meant but i took it to mean that a PC processor has a lot of CPU and not many other cores while an mobile device app processor has not much CPU and a lot of additional cores, with different digital and mixed-signal requirements.
All that IP, which Intel may have in 32-nm HKMG, has to be moved across to 22-nm FinFET.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.