At the end of this article, Peter notes, "ARM processor cores are also supported on a 28-nm fully depleted SOI (FDSOI) process developed by STMicroelectronics NV and being transferred to foundry GlobalFoundries Inc. (Milpitas, Calif.) that is expected to subsequently shrink to 20-nm."
There was some dicussion in the comments here re: multiVT. Thought you might be interested to know what ST has to say about that for its new 28nm FD-SOI ARM-based SOCs:"Planar FD technology allows several methods for setting the threshold voltage VT, including engineering the gate stack work function, trimming the gate length and other process engineering techniques. Thanks to this, STMicroelectronics’ 28FDSOI technology is capable of offering 3 VTs (HVT, RVT, LVT), as in traditional bulk CMOS technologies." (see http://www.advancedsubstratenews.com/2012/04/st-white-paper-excerpts-planar-fully-depleted-silicon-technology-to-design-competitive-soc-at-28nm-and-beyond/)
Also, for a succinct summary of Prof. Fossum's view on SOI for FinFETs (from a few yrs ago, but I believe still valid), see his ASN article http://www.advancedsubstratenews.com/2007/05/a-perspective-on-multi-gate-mosfets/. He concludes:"...the underlying BOX effectively suppresses the source-drain leakage current under the gated fin-body (see the figure). Bulk Si would require heavy doping to suppress this current, as well as to effect reasonable device isolation. But one of our goals with MuGFETs [note: FinFETs are part of the multigate/MuGFET family] is to get away from doping and the random effects it causes: the only pragmatic way to do that is to put the UTB [ultrathin body] FinFET on SOI."
Eetimes article today provides another example of Mr. East point.
PA are one of the hardest RF components to integrate in CMOS and will likely never be integrated into a finfet platform since 3D finFETs degrade RF parameters due to higher parasitic resistance and capacitance.
So when intel sets out to introduce this new chip it uses a foundry 65nm technology.
I don't think a true single chip cell phone with PA (or any RFCMOS chip for that matter) will ever go to a finfet.
Mr. East point was Mobile chips require higher levels of integration ( RF and power transistor being just two examples) which are not even supported today in intels 22nm finfet so process lead means more than Moore law in mobile market. Process lead requires SOC integration.
....I think this was @nc3 point above as well.
No I can't.
I am willing to accept James7740's assertion that Intel's implementation of FinFET is not conspicuously better than planar.
In my defence i did say "may" not "is."
And the point i was tryng to make was not related to FinFET versus planar but with regard to the assertion that Intel FinFET being 30 times worse than reality.
Professor Asenov's simulation indicates that in terms of leakage rectagular-FinFET-on-SOI is 2 to 3.5 times better than rectangular FinFET which is 15 or 20 percent better than triangular FinFETs.
But rectangular FinFET-on-SOI is not yet "reality."
Prof. Fossum, Assanov, and Bokor have all published on this.
Ideal finfet has some advantage. But a real finfet has many compromises so it is very possible real product shows no net advantage.
(1) Higher leakage in Bulk vs SOI (see Fossum work on Bulk having leakage below the fin)
(2) Higher transistor variability (see Borkor's paper "Sensitivity of Double-Gate and FinFET Devices to Process Variations". Intel is not processing fin thickness control, fin doping, or gate oxide thickness to Borkor's requirements so little or no or even a loss in "finfet advantage" is plausible.
Mr East was clearly talking about mobile SOC.
Intel atom is shipping 32nm while arm is shipping 28nm.
I can't see how anyone can argue intel has a technology
advantage for mobile SOC
Regarding your question what ip ivy bridge is missing for mobile SOC? Are you kidding?
Compared to Qualcomm snapdragon MS!8960, ivy bridge is missing (1) power management (lowest power part intel is shipping with 22nm is 17W...~ 10x too high for mobile), (2) integrated LTE, 3G, HSPA (3) GPS, (4) Audio HW, and (5) Multimedia processor just to name a few.
Lastly, same comment I made to Peter relates to your "non finfet process to deal with". Show us one piece of data that shows finfet leakage or performance advantage on the only 22nm part intel is shipping. I think James7740's analysis is correct and is known by many others in the industry
I think james7740 put forth the best quantification of finfet leakage (no improvement over planar / likly even higher). I think most in industry when the look at ivy bridge conclude the same.
So can you put forth like james7740 what data you base your comment
"Intel FinFETs may be the best for leakage performance in the market at present "
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.