Unfortunately ARM CEO is correct.
that is why Intel/Infineon (we) make our mobile ARM SOC at foundry.
Foundry 28nm is better even than Intel 22nm. I know many will not believe but look at back end metal lines. Intel 22nm has CPU metal system that is great for high performance but poor for density.
Intel's 22nm also has much higher leakage, cost, worse analog, worse RF, worse high V transistors in terms of specs and the type of devices offered.
It probably won't be difficult for Intel TD gurus to develop a planar CMOS technology to meet SOC requirement. But it would take time and effort for TD. Besides, mfg. cost in Intel's fabs can't compete with the more cost effective foundry fabs. So why bother, they can use foundry just as well.
Peter, do you know what Warren meant when he speaks extensive range of peripheral circuitry. It seems to imply that Intel could not manufacture SoCs using its FinFet technology due to these circuitry. The IvyBridge processors using FinFet do have PciE intefaces including the analog(ish) serdes and other non-digital PLLs etc integrated. Is there some other type of SoC circuit that is not FinFet friendly?
Either Warren is in a denial mode (i.e. ARM-based SoC is behind Intel) or NC3 wasn't aware of the whole story behind the 22nm at Intel (if I were Intel, I would keep on making the Infineon mobile ARM SOC on foundry because of the risk involved, hence this is no proof of the said issues with Intel 22nm) or people at Intel have been lying through their teeth. Based on the public information, Merrifield is scheduled for release in H2CY2013. This implies that the Merrifield SoC has already been sampled! Warren could be hiring private investigators to validate the birth of Merrifield SoC ;-)
I don't know exactly what Warren East meant but i took it to mean that a PC processor has a lot of CPU and not many other cores while an mobile device app processor has not much CPU and a lot of additional cores, with different digital and mixed-signal requirements.
All that IP, which Intel may have in 32-nm HKMG, has to be moved across to 22-nm FinFET.
SoCs have up to three different voltages with corresponding gate oxide thicknesses. I/O typically uses 0.18 um 3.3 V for example. The finfet cost and complexity has to be included with non-finfet portion for overall SoC process cost-effectiveness consideration.
"East said that Intel's 22-nm FinFET is being used for high-volume PC chips" - Warren East in classic understatement mode omitted to mention that its high *margin* PC chips that Intel is making.
This is all playing out along the lines in Clayton Christensen's book which is well over a decade old now. Intel cannot wean itself off its cash cow, just as Kodak couldn't.
@nc3, Infenion uses foundry to make their SOCs. I am guessing that SOC you mentioned is a older design, designed keeping foundry in mind.Doesn't make any sense to make that at Intel Fab.Cost prohibitive. And if a special process is needed, it will take time to develop,
If you work for Intel now, tell me this, where does Intel makes its periphery chips & SOC for its server & MP chips?
Everybody uses slightly older technology to make Mixed mode or analog chips. They do not always need the latest technology.
This is not an excuse for Digital IP & memory they are designed using latest tech.
Looks like your right.
Intel marketing is "good". They had us believing 10x lower leakage with trigate. Turns out 3x worse. So a factor of 30x marketing versus reality.
Let's see how they market the news when they switch to SOI.
I think you are mis-using the numbers here to get to 30x. It is always important to reference what is being compared against.
Intel 'tri-gate' FinFETs may well be superior to planar bulk CMOS, which is what most other companies are offering at present.
But Intel triangular FinFETs are a few percent inferior to rectangular FinFETs on bulk silicon
And rectangular FinFETs on bulk silicon are 2 to 3.5 times worse than FinFETs-on-SOI, according to GSS. As yet nobody is making FinFET-on-SOI although it may come.
So Intel FinFETs may be the best for leakage performance in the market at present but not quite as good as previously hoped because of triangular cross-section, which may have been adopted for manufacturing reasons.
Here is the data. Intel 22nm device specs were published at vlsi 2012. Leakage current is 1 to 100nA/um. Foundry for mobile 28nm SOC is 10pA/um to 10nA/um. Foundry mobile is 10X to 100X lower depending on device.
Intel will have a finfet soc in market in 2013. Since its not in market we don't know leakage. Intel will improve finfet and improve leakage but my guess it will match foundry leakage (not beat it)
Can you share your reference that intel is shipping lower leakage with finfet than Foundry and what leakage number you are using vs ( 1-100nA/um I ref.)
Intel does not have
Here is some more Intel leakage data. I understand there is confusion in media on this. Another data point on this is from Intel's 22nm product.
See Toms hardware comparing 3.5 Ghz parts idle power increase for 22nm
trigate compared to 32 planar : 71W vs 66W. Transistor leakage is a key component of idle power. see next quote in article as well. "Intel admits that it didn’t do much of anything to cut Ivy Bridge’s power consumption beyond its adoption of 22 nm lithography. It’s not surprising, then, that idle power use doesn’t really change compared to last generation."
So product shows ~ same leakage, ~same performance (3.5Ghz).
Explaining this unexpected result on leakage and performance could be
a great article.
I think james7740 put forth the best quantification of finfet leakage (no improvement over planar / likly even higher). I think most in industry when the look at ivy bridge conclude the same.
So can you put forth like james7740 what data you base your comment
"Intel FinFETs may be the best for leakage performance in the market at present "
No I can't.
I am willing to accept James7740's assertion that Intel's implementation of FinFET is not conspicuously better than planar.
In my defence i did say "may" not "is."
And the point i was tryng to make was not related to FinFET versus planar but with regard to the assertion that Intel FinFET being 30 times worse than reality.
Professor Asenov's simulation indicates that in terms of leakage rectagular-FinFET-on-SOI is 2 to 3.5 times better than rectangular FinFET which is 15 or 20 percent better than triangular FinFETs.
But rectangular FinFET-on-SOI is not yet "reality."
I would expect Mr. East to put his company in the best possible light.
The rest of the story is:
1. Intel is making 22nm FinFET chips now for Win7 and (shipping in October) Win 8 notebooks. I suspect ARM SOC makers would LOVE to get into the couple hundred million notebooks that ship a year if they didn't have a crippled variant of Win 8 and non-FinFET processes to deal with.
2. Those Intel 22nm notebook CPUs also have memory controllers, copious cache, graphics including (I believe) video acceleration and PCIe interfaces. So what's the missing Intel IP?
Peter was right, the ARM camp is behind in process technology. Don't let Mr. East's snappy comebacks fool you.
Mr East was clearly talking about mobile SOC.
Intel atom is shipping 32nm while arm is shipping 28nm.
I can't see how anyone can argue intel has a technology
advantage for mobile SOC
Regarding your question what ip ivy bridge is missing for mobile SOC? Are you kidding?
Compared to Qualcomm snapdragon MS!8960, ivy bridge is missing (1) power management (lowest power part intel is shipping with 22nm is 17W...~ 10x too high for mobile), (2) integrated LTE, 3G, HSPA (3) GPS, (4) Audio HW, and (5) Multimedia processor just to name a few.
Lastly, same comment I made to Peter relates to your "non finfet process to deal with". Show us one piece of data that shows finfet leakage or performance advantage on the only 22nm part intel is shipping. I think James7740's analysis is correct and is known by many others in the industry
Prof. Fossum, Assanov, and Bokor have all published on this.
Ideal finfet has some advantage. But a real finfet has many compromises so it is very possible real product shows no net advantage.
(1) Higher leakage in Bulk vs SOI (see Fossum work on Bulk having leakage below the fin)
(2) Higher transistor variability (see Borkor's paper "Sensitivity of Double-Gate and FinFET Devices to Process Variations". Intel is not processing fin thickness control, fin doping, or gate oxide thickness to Borkor's requirements so little or no or even a loss in "finfet advantage" is plausible.
Eetimes article today provides another example of Mr. East point.
PA are one of the hardest RF components to integrate in CMOS and will likely never be integrated into a finfet platform since 3D finFETs degrade RF parameters due to higher parasitic resistance and capacitance.
So when intel sets out to introduce this new chip it uses a foundry 65nm technology.
I don't think a true single chip cell phone with PA (or any RFCMOS chip for that matter) will ever go to a finfet.
Mr. East point was Mobile chips require higher levels of integration ( RF and power transistor being just two examples) which are not even supported today in intels 22nm finfet so process lead means more than Moore law in mobile market. Process lead requires SOC integration.
....I think this was @nc3 point above as well.
At the end of this article, Peter notes, "ARM processor cores are also supported on a 28-nm fully depleted SOI (FDSOI) process developed by STMicroelectronics NV and being transferred to foundry GlobalFoundries Inc. (Milpitas, Calif.) that is expected to subsequently shrink to 20-nm."
There was some dicussion in the comments here re: multiVT. Thought you might be interested to know what ST has to say about that for its new 28nm FD-SOI ARM-based SOCs:"Planar FD technology allows several methods for setting the threshold voltage VT, including engineering the gate stack work function, trimming the gate length and other process engineering techniques. Thanks to this, STMicroelectronics’ 28FDSOI technology is capable of offering 3 VTs (HVT, RVT, LVT), as in traditional bulk CMOS technologies." (see http://www.advancedsubstratenews.com/2012/04/st-white-paper-excerpts-planar-fully-depleted-silicon-technology-to-design-competitive-soc-at-28nm-and-beyond/)
Also, for a succinct summary of Prof. Fossum's view on SOI for FinFETs (from a few yrs ago, but I believe still valid), see his ASN article http://www.advancedsubstratenews.com/2007/05/a-perspective-on-multi-gate-mosfets/. He concludes:"...the underlying BOX effectively suppresses the source-drain leakage current under the gated fin-body (see the figure). Bulk Si would require heavy doping to suppress this current, as well as to effect reasonable device isolation. But one of our goals with MuGFETs [note: FinFETs are part of the multigate/MuGFET family] is to get away from doping and the random effects it causes: the only pragmatic way to do that is to put the UTB [ultrathin body] FinFET on SOI."
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