I will give another reason why the ultra-thin 6nm or below Si channel transistor might not work by device physics point view. Suppose for the sake of argument that Soitec could provide the 6-nm thin Si channel layer. For the transistor with such extremely thin channel, the quantum confinement will be dominant. It means in simple terms that the channel electrons don’t behave like particles any more, but instead act like electron waves. As a result, drift and diffusion based classical semiconductor physics and electron particle based Maxwell-Boltzmann statistics are no longer applicable. Instead, the electron behavior is now described by the quantum mechanical physics based Schrodinger’s wave equations and is subjected to Heisenberg’s uncertainty principle. As a result, we will observe a large variation in transistor parameter measurements such as Vt, Id/Vg, Id/Vd, DIBL, SS(sub-threshold slop) and SRAM noise margins. Therefore, in my opinion the 20/22-nm FD SOI with 6-nm of Si layer will not be manufacturable. IBM has spent too much and too long on FD SOI. S. Kim
For the first time I attended the SOI Conference held on October, 2011 at Phoenix, Arizona, because I live in Phoenix. I am the guy who asked the presenter whether Soitec can supply a reliable 6-nm ultra- thin Si channel layer, he said yes. I did not ask the question in term of self-heating, but in terms of the manufacturability because if Soitec can’t provide the 6-nm Si layer, then you have to live with self-heating. Soitec is the largest SOI wafer supplier. The registration materials contained a pamphlet entitled “ADVACED SUBSTRATE NEWS” by Soitec for the conference attendees. In page 9 of the pamphlet, Mr. Bonnin, Product Integration manager states that the roadmap for FD-SOI requires wafers with ultra-thin top silicon that is un-doped and ultra-thin BOX. Soitec is ramping in production these wafers for high volume manufacturing for the 20/22nm nodes. For these nodes, the thickness of the ultra-thin top Si is 12nm and the ultra-thin BOX is 25nm, not the 6nm silicon layer that I questioned! The 6nm is one-half of the thickness (12nm) that is manufacturable by Soitec for the 20/22 nm FD-SOI technology nodes. At the 2012 VLSI Symposium several papers on FD-SOI MOSFETs with Si thickness of 6.5nm and 7nm were presented by IBM and Its International Alliance members. The 6.5/7nm Si thickness data are test chip data, not manufacturable yet by Soitec. S. Kim
I try to answer your comments:
1. Even from practical design standpoint, FD-SOI is different from PD-SOI, and definitely different from Bulk-Si. To save my time I recommend a book entitled,” SOI Circuit Design Concepts” by K. Berstein and N.J. Rohrer, Both IBMers. They are primarily SOI circuit designers. Read specially chapter 3. They show how to minimize the self-heating effect (P55/181) and floating body effect by the means of circuit designs (P196).
2. OKI had FD-SOI LSIs for low power and low performance for long time ago are immaterial here because we are now at ultra- low power and ultra-high performance Bulk Si based 28 and 22-nm technology era. Intel’s Bulk-Si based FinFETs have been in high volume manufacturing for several months, and is reported that Microsoft Windows 8 PRO based tablets and ultrathin note books will be available in this quarter. Could OKI do it today? Why the FD SOI claimed to be so much superior to Intel’s FinFETs on bulk Si is not in volume manufacturing today?
3. Your FD-SOI transistor now consists of ultra-thin BOX (6nm or less) to prevent self-heating and ultra-very thin si (possibly also 6-nm) to prevent the floating body and short channel effects. I very doubt that Soitec can put a 6-nm BOX layer and another 6-nm Si layer on top of the thin BOX in a manufacturing environment. I have more to say about self-heating in your reply to Kris.
4. The FD on SOI versus FinFETs on Si is not just leakage current issue. It is mainly manufacturability. It is not so difficult to have the punch-through stop implants on the silicon surface beneath the fins. Intel’s 22-nm FinFETs on bulk Si is published in June, 2012 VLSI Symposium. Lastly, it is recently reported that UMC has worked out a licensing deal with IBM for its 20-nm FinFETs process, but the process UMC has licensed is for FinFETs on Bulk-Si, not on SOI . Doesn’t that surprise you? TSMC has been developing bulk 20-nm FinFETs for several years, and published ain 2010 IEDM. S. Kim
Hi Kris, you might want to check out a Leti paper from the last SOI Conference -- you can get it from the IEEE Xplore site: "Self-Heating Effects in ultrathin FD SOI transistors", N. Rodriguez et al. Having run real silicon (advanced 22nm SOI transistors with 6nm of Si film thickness) at Leti, they say, "...we can conclude that SHE does not represent a limiting factor for the reliability of ultrathin FDSOI transistors, in
particular for fast switch operation." cheers.
@michigan, the following information can be found in the FD-SOI section on the SOI Consortium website:
1. In fact there is no floating body / history / kink effect in FD-SOI (or ET-SOI, as IBM calls it) or FinFET on SOI (which is also a fully-depleted technology). That was strictly a PD-SOI issue. From a practical design standpoint, FD-SOI is no different from bulk.
2. Oki (now calling itself Lapis) has been in high volume production of FD-SOI for over a decade -- see http://www.advancedsubstratenews.com/2008/05/oki-the-industry%E2%80%99s-commercial-fd-soi-pioneer/
3.In the ultra-thin BoX (insulating Buried Oxide) version of FD-SOI (which is what STMicro is using) it's so thin that for practical purposes it's not really different from bulk in terms of self-heating -- see Question 11 in the SOI Consortium's FD-SOI Q&A:
4.FinFETs are part of the MuGFET (multi-gate FET) family, first proposed Hitachi in 1989 (D. Hisamoto, T. Kaga, Y. Kawamoto, E. Takeda: A fully depleted leanchannel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET. Technical Digest of IEDM, pp. 833-836 (1989)). When Chenming Hu presented the FinFET in 1999, it was on SOI. In fact, most research on multigate devices was conducted on SOI until Samsung presented a way to do them on bulk in 2003. As Chenming Hu himself pointed out in a recent article, "FinFET on bulk requires heavy implant below the fin to suppress leakage and that requires tradeoffs with FinFET performance. When built on SOI, the FinFET does not suffer from leakage below the fin. Building FinFETs on SOI also confers certain advantages in simplifying manufacturing." (See http://www.advancedsubstratenews.com/2012/04/chenming-hu-soi-can-empower-new-transistors-to-10nm-and-beyond/
I agree with @michigan. SOI suffers from self-heating problems, this is intrinsic to its structure (oxide not conducting heat well) and there is no good way around it...I doubt whether Professor Asenov's sims take into account thermal effects but could be wrong...kris
The SOI technology was developed by IBM; PD(partially depleted), FD(fully depleted), and ET(extremely thin) SOI. IBM developed successfully PDSOI technology based products such as 165nm, 95nm, 65nm but no product based on FD and ET SOI technologies has been developed yet although enormous resources have been spent by IBM and its international alliances for long time. This is in my opinion because there are two major problems inherently associated with FD and ET SOI, floating body effect and self-heating. FinFET on SOI doesn’t remove the floating body effect and self-heating. So called “Kink effect” induced by hot carriers occurs in Id/Vd transfer characteristics or non-saturation current behavior. Besides, ETSOI has a manufacturability issue. The self-heating; the FinFET on SOI is completely surrounded by gate oxide at the top, SiO2 at the bottom and isolation SIO2 at the sides. As a result, a significant amount of heat can be generated by even single transistor measurements such as Id/Vd with Vg as a parameter simply because the SiO2 substrate is a very poor heat conductor compared with the Si substrate. The heat generated can have detrimental device impacts as well as circuit operation such as degradation in transconductance and mobility, high source/drain resistance, and high leakage current. I would like to see real data, not just simulated one because Intel’s FinFET is at high volume manufacturing for some time. I doubt Intel would adopt FinSOI at 14nm. Sang Kim
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