@michigan -- not sure why there's this misunderstanding -- all the current literature that I've seen indicates that there is *no* floating body (FB) / history etc. effects in FinFETs on SOI. FinFETs -- whether on bulk or SOI -- are a fully depleted technology. FB/history effect is strictly a PD (partially depleted)-SOI phenomenon. IBM, btw, is sticking with PD-SOI for their high-perf big iron until they make the switch to FinFETs on SOI at 14nm. The SOI Consortium contends that in fact FinFETs on SOI are easier to manufacture -- cutting up to a year off the mfg learning curve, and that that plus fewer process steps ultimately makes the SOI version cheaper. SHE (self-heating effect) is a challenge for FinFETs in both SOI and bulk. FinFETs are part of the MuGFET family of vertical structures, which has been studied since Hitachi first proposed them (on SOI!) in 1989. As such, the industry's been working on vertical structures like FinFETs for over two decades. The research and development has very deep roots....
Recently professor Asenov of GSS pointed out the disadvantages of the bulk based Intel’s 22-nm FinFET and superiorities of FinFETS on SOI, citing 50% less leakage current, smaller variability, and not extendable to 14-nm without SIO substrate….etc. However, the FINFETon SOI may be not even manufacturable as I commented in “FinFETs-on-SOI can double battery Life, says GSS”, 7/27/2012, EE Times News. The two problems intrinsic to FinFETs on SOI are floating body effect and self-heating that need to be overcomed. UMC licensed IBM technology for 20-nm FinFETs, but the process UMC has licensed is for FinFETs on bulk silicon rather than on SOI wafers. This is rather surprising since IBM has always promoted FinFETs on SOI. TSMC has been developing bulk 20-nm FinFETs for several years, and published its transistor transfer characteristics at 2010 IEDM. I doubt that UMC can beat TSMC on bulk based FinFET technology development race. Tsmc is at least three years ahead of UMC in 20-nm bulk technology. S. kim
Spot on. Intel's metal system is only on par with foundry 28nm and that largely set SOC die size. Bottom line intel 22nm will not be cost competitive for mobile SOC. This along with intel 22nm (at present time) not supporting adequate SOC device types and the technology having a lot of variation issues (from the sloped fins causing gate oxide and WF variation) is what the industry assessment is at this time.
Lithographically, foundry's 28 nm should be close to Intel's 22 nm at about 45 nm half-pitch.
But the fin process adds extra cost without helping transistor density. I'd be curious if foundry 28 nm transistors perform so poorly against Intel's 22 nm FinFET.
TSMC refers to their first FinFET process as 16-nm.......but ASML and UMC have both said that regardless of that these initial foundry FinFET processes are called they will be the application of FinFET front-end processing to the same back-end interconnect used at 20-nm
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.