This article is wrong in a key way. The article said that in Class 0, the Sync* input is not used. This is not true. In class 0, the Sync* signal is still used to transition from Sync comma characters (K28.5) to the Initial Lane Alignment Sequence (ILA). Assuming the Sync* signal is distributed with equal skew to multiple ADC's, and they have a common sampling clock, they will all start at the same time.
Class 1 and 2 are primarily used to ensure that the latency from an ADC to an output DAC is determined and known. For many ADC only applications it is not important to exactly know the latency - only that all the ADC's are time aligned.
For ADC's the standard works this way:
1. The ADC starts with Sync* low. This forces it to output K28.5 comma characters, encoded 8B10B to transmit both clock and data in the one serial data stream.
2. The FPGA serdes input locks onto the 8B10B encoded input, and starts clock and data extraction.
3. A word aligner searches the data stream for the K28.5 comma character.
4. Once 4 comma characters have been received, the receiver is locked. It de-asserts Sync*.
5. The ADC waits until the next frame boundary (for Class 0) or the next LMFC boundary (for Class 1 or 2) and outputs the ILA sequence, which is 4 multiframes of pre-specified length (at least 18 frames). The second multiframe frame includes the JESD204B 14 octets of link configuration data from the ADC (including Device, Bank and Lane ID numbers, Lanes per device (L), Octets per frame (F), Octets per multiframe (K), number of converters per device (M), converter resolution, etc).
6. After the ILA ADC sample values are output.
If class 1 or 2 are used, the ADC outputs data in synchronism with LMFC counter that establishes the start of the multiframe.
The JESD204 standard is intended for an ADC/DAC interfaced to FPGAs/ASICs. I am not sure it would viable for general chip to chip interconnect since it is specified around converter data and system requirements encountered when dealing with converters. Perhaps it could be adapted though. Maybe we will see a standard for general interconnect evolve out of the JESD204 spec...
do you see 204 penetrate into additional domains other than analog front ends?
what about interface to optical drivers?
what about chip to chip interconnect? having it already on FPGA can facilitate it. standard like that can help IC interfacing.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.