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mcgrathdylan
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re: FPGA vendors squabble over 28-nm market share
mcgrathdylan   8/3/2012 1:29:44 AM
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That should be "supports the theory that the business of ASICs is at its sunset."

KB3001
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re: FPGA vendors squabble over 28-nm market share
KB3001   8/3/2012 12:32:53 AM
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Without a doubt. FPGAs are not succeeding on the other side of the spectrum however with the rise of GPGPUs.

krisi
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re: FPGA vendors squabble over 28-nm market share
krisi   8/2/2012 8:03:58 PM
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I think the flight to FPGA is pretty obvious, it is enough to check the number of ASIC starts annually...Jack is clearly biased as he is trying to promote eSilicon service so you can't blaming to claim otherwise...Kris

mcgrathdylan
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re: FPGA vendors squabble over 28-nm market share
mcgrathdylan   8/2/2012 7:48:13 PM
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Jack Harding, president and CEO of eSilicon Corp., is a well-known skeptic of the notion that FPGAs are displacing ASICs. http://www.eetimes.com/electronics-blogs/eda-designline-blog/4033356/A-dissenting-opinion-on-the-programmable-imperative- Gavrielov said during an interview earlier this year that he respects Harding and his opinion, but that the success of fabless ASIC vendors or "value chain producers" like eSilicon does not mean there is not a flight to FPGAs. On the contrary, Gavrielov argues, as the cost of doing an ASIC skyrockets, firms look first to outsource them and then, eventually, to skip them altogether and go with FPGAs. The success of Xilinx and that of eSilicon is not mutually exclusive, he argues. But, according to Gavrielov, the success of eSilicon and others like it supports the business of ASICs is at its sunset.

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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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