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DrFPGA
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re: Terasic, Altera FPGA-based boards for high-frequency trading
DrFPGA   8/21/2012 11:02:35 PM
NO RATINGS
When I was looking at the details of financial number crunching applications on FPGAs the limiting factor always seemed to be the memory interface. Going on and off chip for big chunks of memory to feed the calculation engines was an issue. If the memory access was predictable (like an FFT) you could always pipeline things, but financial calculations required indirections and the resulting additional access time was a killer. Maybe new algorithms are available now to minimize this effect. Anyone out there have an update (or is it too secret to tell..).



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