I had come up with the exact same symmetrical TIS design as Samuel, independently, which I confirmed by corresponding with Samuel after the article was published in Linear Audio, before seeing the article my self. So I have to agree it is a clever design : - ).
My only reservation with Samuelsís article is that it did not venture into a loop gain analysis of the Miller compensation loop. As some might find it of use Iíve uploaded some of my own analysis, including detail of an alternative method (shunt compensation) of predictably stabilising the Miller compensation loop, onto the net here:
Nice circuit, but not really new. There are also some disadvantages not mentioned unfortunately. The slew limit from input stage and Q11/12 remains. The mid-stage Q9 can easily drive Q11 too hard (Q11 then in cut-off!). Here better add a clamping circuit. Allmost all transistors need to withstand high-voltages and the signal has to travel through many stages, that makes the whole amp quite unstable. The older mentioned circuit can be also improved to get rid some the mentioned limitations. For instance the filtering for ripple rejection is quite easy to implement with little effort.
Blog Doing Math in FPGAs Tom Burke 18 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...