Around 10 nm, you cannot merely have a radically new technology come in for one area but a whole package of technologies needed for devices, interconnect, etc. Plus we are now at the scale of electron mean free paths.
Yes, question is not if 10nm can be done but what economic advantage does it bring after spending Billions and Billions of $. With 80nm pitch used for 22nm that would mean ~40nm metal pitch for 10nm. There is no cost effective way to print. Plus even if lithography breakthrough, parasitic capacitance and line resistance are going to be so large chips will be slower and higher power.
I have no doubt that Intel can get to 10 nm with quadruple patterning, but will they be able to suppport a reasonable business model once they get there? And what happens after 10 nm? Is that the end of scaling unless and until EUV litho kicks in at reasonable cost?
In his talk, Bohr said many features in the 22nm process use 80 pitch features, a size chose for this generation because they can be single patterned.
He did not say anything about double patterning at 22nm or quintuple patterning on any process.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.