In theory Intel’s Trigate FinFETs can extend to 10nm beyond as long as lithography can permit because for FinFETs to be fully depleted to suppress the leakage current or short channel effects the fin width (W) less than gate length (Lg) is only required. For 10nm node and below, however, new physical phenomena not seen in wide fin W will occur. The fin W at bottom of the fin for 10nm node and below may approach 6nm or less and 5nm at top of the fin. However, for the fin W with such an extremely thin 6nm may hit the CMOS scaling wall or the end of the Moore’s Law because of the quantum mechanical effects imposed by the structural quantum confinement. It means in simple terms that the electrons within such extremely thin 6nm fin W do not behave like classical particles any more, but instead act as waves. As a result, drift and diffusion based classical semiconductor physics is no longer applicable. Instead, the electron behavior is now described by the quantum mechanical physics based Schrodinger’s wave equations and is subjected to Heisenberg’s uncertainty principle.
The impact of such quantum confinement on the electrical characteristics is a significant increase in threshold voltage Vt due to the mobility degradation caused by decrease in the inversion layer thickness. The Vt increase depends on how thin the fin W is. But this adds to the variation in Vt due to the short channel effect with varying Lg. The other more critical effect is very large variations or uncertainties in transistor transfer characteristics such as Vt, Id/Vg, ID/Vd, DIBL, SS (sub-threshold slop), and SRAM noise. These are physical limits derived from quantum mechanical effects, limiting to the channel length to 10nm node with fin W of 6nm. Process variations not considered here could further adversely impact the variability of finFETs electrical characteristics. Therefore, in my opinion the 10 nm node with fin W 6nm or less will not be manufacturable or the end of CMOS scaling. S Kim
For the cost-effective part to make sense, we need the half-pitch or the distance between metal wires to shrink, to enable more transistor connections per unit area. If this distance does not shrink, but only a particular feature shrinks, it could actually add process complexity and some cost.
I believe that this is a fairly standard tactic. The process node only identifies the smallest feature that can be reliably resolved and patterned. There shouldn't be any roadblock to making a 90nm sized transistor in 20nm but I'm not a chip designer. Anyone out there that can comment?
Slowed scaling just means that more emphasis has to be put on other aspects of the design. We won't be able to rely on just buying the latest and greatest piece of silicon. Personally I think this is going to be great motivation for better understanding of hardware and the implications of poor coding/software design.
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