In his talk, Bohr said many features in the 22nm process use 80 pitch features, a size chose for this generation because they can be single patterned.
He did not say anything about double patterning at 22nm or quintuple patterning on any process.
I have no doubt that Intel can get to 10 nm with quadruple patterning, but will they be able to suppport a reasonable business model once they get there? And what happens after 10 nm? Is that the end of scaling unless and until EUV litho kicks in at reasonable cost?
Yes, question is not if 10nm can be done but what economic advantage does it bring after spending Billions and Billions of $. With 80nm pitch used for 22nm that would mean ~40nm metal pitch for 10nm. There is no cost effective way to print. Plus even if lithography breakthrough, parasitic capacitance and line resistance are going to be so large chips will be slower and higher power.
Around 10 nm, you cannot merely have a radically new technology come in for one area but a whole package of technologies needed for devices, interconnect, etc. Plus we are now at the scale of electron mean free paths.
Slowed scaling just means that more emphasis has to be put on other aspects of the design. We won't be able to rely on just buying the latest and greatest piece of silicon. Personally I think this is going to be great motivation for better understanding of hardware and the implications of poor coding/software design.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.