I think 20 nm won't be popular for a while. It is also quite possible some will go direct from 28 nm to 14 nm, after a few years. If the patterning technology is quite expensive, you'd need to make up with higher density sooner.
Ah but if we prevented development of 16-nm/14-nm and 10-nm nodes until all the 28-nm to 20-nm transition problems were solved, the industry would be severely delayed in ever getting to 16/14-nm.
Working on multiple challenges and production nodes has been with us for a long time and one of the ways in which Moore's predictive law has been fulfilled....to date.
"FinFETs in bulk silicon are more trouble than they are worth", Horacio Mendez,
...that does look to be the case for the "16nm node" which is "20nm design rule finfet on bulk silicon".
I can't see doing a SOC in FinFET unless a planar device is also offered for all my analog/mixed signal circuits and low leakage always on circuits.
How about we not talk as an industry about 10nm or 14nm until we admit at even today at 20nm will still don't have a viable 20nm strategy. Today's 20nm due to the double patterning just does not offer much if any improvement over 28nm.
Even over the next 5 years it does not appear cost per transistor will be lower in 20nm vs 28nm.
I do hear foundry has found many issues with Intel's 22nm bulk Fin design point for SOCs. Top issues is supporting range of threshold voltages required for SOCs. Intel's approach which dopes the fins causes too much leakage variation and matching issues for circuit operation less than 0.9-1V supply voltage.
This is all consistent with Intel's own 22nm SOC now delayed until end of 2013. Rumor is Intel might be going to SOI for 22nm SOC technology version to fix this issue. Would allow intel to implement a real undoped body FinFET.
Blog Make a Frequency Plan Tom Burke 17 comments When designing a printed circuit board, you should develop a frequency plan, something that can be easily overlooked. A frequency plan should be one of your first steps ...