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Brian.Fortman
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re: TI introduces new SafeTI MCUs and PSU for safety-critical apps
Brian.Fortman   9/25/2012 2:55:25 PM
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TI’s lockstep implementation is a 1oo1D design which is inherently less sensitive to common cause failure than 1oo2 or 2oo2 lockstep architectures. In addition TI has applied measures including temporal diversity and physical/layout diversity to further mitigate common cause failure concerns. TI has been producing products with similar lockstep architectures for many years and has yet to see a confirmed common cause CPU failure. Details of the design for mitigation of common cause failure in the lockstep diagnostic are publicly available Section 5.7.1.1 in the RM46 safety manual, which can be downloaded from http://www.ti.com/hercules (lit#SPNU551)

imi121
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re: TI introduces new SafeTI MCUs and PSU for safety-critical apps
imi121   9/25/2012 8:21:29 AM
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How can the lock step cater fro the common cause failures in the RMxx series MCU's



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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