I think I am the guilty one here, not articulating this whole "design" process well in the story.
I will correct the story accordingly. Meanwhile, here's an e-mail I just received from Rockchip's Chen. He clarified this for us as follows:
"What I meant was, after we got the chip, we were able to get the chip in end products in less than 2 months."
Another very informative article - many thanks.
I do have an interesting question - since you are quoting Rockchip's CEO:
The RK31xx is a dual core Cortex A9 product designed for tablets and smartphones. Using Globalfoundries' high-k 28-nm process, “we can reduce cost, gain performance, but most importantly, we will reduce power consumption for tablets,” said Chen
Will the package interconnect for this application processor be Cu-wire wirebond or flip-chip bumps? I am curious how much wirebond for multi-core application processors even in 28nm.
Many thanks in advance if you can find and provide the answer.
Rockchip outsources most of the design work to GUC which is a TSMC affliate. My sources told me it usually takes 3 iterations (sometimes 4) to get it right. So the March to May time frame could be the 3rd try, which could be a simple metal change, or from MPW shuttle to full-mask.
It is amazing to finish a chip design in just 2 months (started a chip in March, showed it in trade show in April and then shipped the samples in May). How much faster can they shorten the design cycle? I have no idea how innovation can take place if there is just little time for chip design to sit down to work, not even think. Personally, I don't think this can help the company to grow healthily and such strategy can't last long.