Something they should have known. So much more energy absorbed from a shorter wavelength photon into a smaller space, obviously higher energy density needs to be dissipated into a larger volume to avoid unwanted material changes.
In one form or another, multiple patterning becomes necessary.
This has been known for years @resistion...I attended IEDM conference 20 years ago where this issue was discussed ;-)...talks about slowing of the Murphy's law started shortly after "the law" was established...I remember limits at 1 micron level considered insurmountable ;-)...but it might be true this time around...litho is clearly a huge challenge...but not the only one...Kris
Wow, that's quite a while back, if I read those papers, maybe I would have reconsidered joining this field, who knows ;-)
I guess saying scaling won't happen would be much riskier than saying a particular way of scaling won't happen.
"Without EUV, Intel believes it will have to write as many as five immersion patterns on a chip which will take more time and money but is still economical." Hope it is true. But when litho rework rate boomed with strigent process requirements in triple and above patterning, process window and yield are impaced severely. It will be hard to see economic advantages in dimension shrinking. It is happening in current 22/20nm processes(double pattern) and getting worse for 14nm and beyond. That is the reason why Intel/Samsung/TSMC(even nVidia) are urging 450mm progress in parallel to lower down process cost. Tons of hurdles ahead, Go engineers.
The EDA enablement of multi-patterning provides a path to maintain a path along Moore's law. The only hesitation has been cost. But what most people are ignoring is the fact that by the time they get an EUV system capable of the numbers they need it will probably cost more than multi-patterning with traditional steppers, and it may even need multi-patterning itself.
would it not be better to make a larger step and go to directed self-assembly (DSA)? multi-patterning feels very incremental with some gains due to smaller feature size and some losses due to lower throughput
The dimensional scaling is clearly reaching demising return and escalating challenges. The NV NAND vendor have recognized it and are shifting to monolithic 3D (see Blog piece by Israel Beinglass http://www.monolithic3d.com/2/post/2012/10/3d-nand-opens-the-door-for-monolithic-3d.html)
The logic vendor would sooner or later recognize it too (especially as the would need to carry the burden all by themselves)- the future of scaling is up - monolithic 3D
A Book For All Reasons Bernard Cole3 comments Robert Oshana's recent book "Software Engineering for Embedded Systems (Newnes/Elsevier)," written and edited with Mark Kraeling, is a 'book for all reasons.' At almost 1,200 pages, it ...