This technique is not suitable for applications which have signal components at very different input levels. As your mention, when one of the gain paths saturates, the signal will be sourced from a lower gain non-saturated path. It is important to note that the saturated ADC must still recover quickly when the signal is back within its range.
I wonder how the system avoids over-drive/saturation of the mid-range and low-end ADCs when a very strong signal (within the high-end range) is present at the very input before the split, for example in a broadband multi-carrier scenario where multiple different narrowband signals may get into the system each with very different input levels.
Or probably the application as discuss by Mr. Fifield is for a single wideband signal therefore saturation of the lower-end ADCs can be discarded.
Anyway, very interesting setup.
More than two decades ago I got into a similar problem for current measurement in an energy meter requiring high dynamic range. I easily solved the problem by using a programmable gain amplifier using analog switches and an op-amp. It worked like a charm for such a slow speed application using a home grown double sided board.
Quick question on footnote :
"The calculation for ENOB is: (dynamic range – 1.76)/6.02"
I've never seen this equation before: Is it specific to the system, or does this apply to any number of ADC's?
The design and test of this stacked ADC is quite interesting. To perfect this the analog gain amplifiers need to have very good matching in phase and amplitude. Probably i feel that if there is a control with feed back between these gain stages in the stacked system the performance may be further improved.
A few years ago I had a problem digitizing heading rate for a robot. Then I realized I needed heading data in two distinct modes. When traveling in a straight line I needed high resolution heading rate data near zero. When the robot was turning I needed low resolution data over the full voltage range.
I easily solved the problem by using two 8 bit A/D channels on the same input, one through a clamped x32 amplifier. When turning I used the non-amplified signal. When traveling straight I used the amplified signal.
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...