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chipmonk0
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CEO
re: TSMC taps ARM's V8 on road to 16 nm FinFET
chipmonk0   10/17/2012 3:48:22 PM
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Rick : Couple questions about the TSMC 2.5-D Test vehicle you have reported. What was the footprint of the whole thing ( with 4 chips ). Did they give any reason why such a 2.5-D module will be better than current modules / packages used in Smart Phones / Tablets ? Thx

any1
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CEO
re: TSMC taps ARM's V8 on road to 16 nm FinFET
any1   10/17/2012 1:50:22 PM
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Double patterning does add a significant amount of complexity to the entire process. And those companies that can do it well will be rewarded. This is where the more vertically integrated companies like Intel and Samsung have an advantage since they can control everything in house. I'm amazed that the foundries like TSMC can execute as well as they do now. But integrating FinFETs, etc. will only make it even more complex to manage in the future. Getting first pass success will become more difficult, and the number of designs at the leading edge will become fewer. Both of these trends are being acclerated by the requirements (costs) of double patterning.

resistion
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CEO
re: TSMC taps ARM's V8 on road to 16 nm FinFET
resistion   10/17/2012 12:56:10 AM
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Intel has used double-exposure techniques for its alternating PSM patterning for the poly gate layer starting at 65 nm. Probably multi-patterning on a few layers should be nothing to them now. The question is if they can handle additional layers such as metal 2/3 requiring double patterning.

rick merritt
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Author
re: TSMC taps ARM's V8 on road to 16 nm FinFET
rick merritt   10/16/2012 11:31:30 PM
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I'd love to hear any real world experiences dealing with chip designs that use double patterning. I hear it ain't easy.

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