Even at 14 nm node, there will be more double patterning layers than multi-patterning layers for sure.
ASML has already said EUV would only be introduced on a few layers, allowing mix-and-match with immersion, but by that time, even the middle layers would be requiring double patterning.
They did not give size of the chip. But Hou did say the test run with Wide IO was only to test out the various aspects of the process and the Wide IO IP which would actually be used with a through silicon via stack in commercial chips.
Worse yet, at least some expect 10 nm may require double patterning even for EUV.
And still worse yet, the EUV throughput is still far short of target, so ASML has acquired Cymer. Apparently, they've scuttled their other EUV source vendor options.
Couple questions about the TSMC 2.5-D Test vehicle you have reported. What was the footprint of the whole thing ( with 4 chips ). Did they give any reason why such a 2.5-D module will be any better than current modules / packages used in Smart Phones / Tablets ?
Blog Doing Math in FPGAs Tom Burke 7 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...