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de_la_rosa
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
de_la_rosa   10/20/2012 9:06:39 PM
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maybe the last presentation we will see from a big player. Beyond 14nm node, is impossible. Unless electron-beam lithography has something under their sleeve?

marcos83
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
marcos83   10/19/2012 11:42:34 AM
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I think this industry is stalling due to the limitations of resolution. The big players have relied on Moore's law as the backbone of their road-map.

chipmonk0
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
chipmonk0   10/18/2012 4:04:26 PM
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Thx

double-o-nothing
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
double-o-nothing   10/18/2012 3:58:51 PM
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Even at 14 nm node, there will be more double patterning layers than multi-patterning layers for sure. ASML has already said EUV would only be introduced on a few layers, allowing mix-and-match with immersion, but by that time, even the middle layers would be requiring double patterning.

rick merritt
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
rick merritt   10/18/2012 12:17:55 AM
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Oh, and the TSVs are supposed to provide much greater bandwidth than today's wire bonded stacks

rick merritt
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
rick merritt   10/18/2012 12:17:16 AM
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They did not give size of the chip. But Hou did say the test run with Wide IO was only to test out the various aspects of the process and the Wide IO IP which would actually be used with a through silicon via stack in commercial chips.

rick merritt
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
rick merritt   10/18/2012 12:15:41 AM
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Intel's Mark Bohr has already said he is considering quad patterning immersion at 10nm. See http://www.eetimes.com/electronics-news/4396146/Intel-sees-quad-patterned-path-to-10-nm-chips

resistion
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
resistion   10/17/2012 10:36:45 PM
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With a wavelength of 13.5 nm and NA of 0.33, 10 nm corresponds to k1 less than 0.25, so indeed the current NXE:3300 won't be useful for very long.

resistion
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
resistion   10/17/2012 9:48:15 PM
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Worse yet, at least some expect 10 nm may require double patterning even for EUV. http://semimd.com/blog/2012/09/17/will-euv-miss-another-node/ And still worse yet, the EUV throughput is still far short of target, so ASML has acquired Cymer. Apparently, they've scuttled their other EUV source vendor options. http://semimd.com/blog/2012/10/17/asml-to-acquire-cymer/

chipmonk0
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
chipmonk0   10/17/2012 3:49:17 PM
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Rick : Couple questions about the TSMC 2.5-D Test vehicle you have reported. What was the footprint of the whole thing ( with 4 chips ). Did they give any reason why such a 2.5-D module will be any better than current modules / packages used in Smart Phones / Tablets ? Thx

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