Even at 14 nm node, there will be more double patterning layers than multi-patterning layers for sure.
ASML has already said EUV would only be introduced on a few layers, allowing mix-and-match with immersion, but by that time, even the middle layers would be requiring double patterning.
They did not give size of the chip. But Hou did say the test run with Wide IO was only to test out the various aspects of the process and the Wide IO IP which would actually be used with a through silicon via stack in commercial chips.
Worse yet, at least some expect 10 nm may require double patterning even for EUV.
And still worse yet, the EUV throughput is still far short of target, so ASML has acquired Cymer. Apparently, they've scuttled their other EUV source vendor options.
Couple questions about the TSMC 2.5-D Test vehicle you have reported. What was the footprint of the whole thing ( with 4 chips ). Did they give any reason why such a 2.5-D module will be any better than current modules / packages used in Smart Phones / Tablets ?
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.