Intel has used double-exposure techniques for its alternating PSM patterning for the poly gate layer starting at 65 nm. Probably multi-patterning on a few layers should be nothing to them now. The question is if they can handle additional layers such as metal 2/3 requiring double patterning.
Double patterning does add a significant amount of complexity to the entire process. And those companies that can do it well will be rewarded. This is where the more vertically integrated companies like Intel and Samsung have an advantage since they can control everything in house. I'm amazed that the foundries like TSMC can execute as well as they do now. But integrating FinFETs, etc. will only make it even more complex to manage in the future. Getting first pass success will become more difficult, and the number of designs at the leading edge will become fewer. Both of these trends are being acclerated by the requirements (costs) of double patterning.
Couple questions about the TSMC 2.5-D Test vehicle you have reported. What was the footprint of the whole thing ( with 4 chips ). Did they give any reason why such a 2.5-D module will be better than current modules / packages used in Smart Phones / Tablets ?
Couple questions about the TSMC 2.5-D Test vehicle you have reported. What was the footprint of the whole thing ( with 4 chips ). Did they give any reason why such a 2.5-D module will be any better than current modules / packages used in Smart Phones / Tablets ?
Worse yet, at least some expect 10 nm may require double patterning even for EUV.
And still worse yet, the EUV throughput is still far short of target, so ASML has acquired Cymer. Apparently, they've scuttled their other EUV source vendor options.
They did not give size of the chip. But Hou did say the test run with Wide IO was only to test out the various aspects of the process and the Wide IO IP which would actually be used with a through silicon via stack in commercial chips.
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