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double-o-nothing
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
double-o-nothing   10/18/2012 3:58:51 PM
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Even at 14 nm node, there will be more double patterning layers than multi-patterning layers for sure. ASML has already said EUV would only be introduced on a few layers, allowing mix-and-match with immersion, but by that time, even the middle layers would be requiring double patterning.

chipmonk0
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
chipmonk0   10/18/2012 4:04:26 PM
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Thx

marcos83
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
marcos83   10/19/2012 11:42:34 AM
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I think this industry is stalling due to the limitations of resolution. The big players have relied on Moore's law as the backbone of their road-map.

de_la_rosa
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re: TSMC taps ARM's V8 on road to 16 nm FinFET
de_la_rosa   10/20/2012 9:06:39 PM
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maybe the last presentation we will see from a big player. Beyond 14nm node, is impossible. Unless electron-beam lithography has something under their sleeve?

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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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