Its very interesting, but i'm skeptical of the usefulness. The thing is that the cores are going to be starved for data. Maybe you can pick a few specific applications where this may not be the case, but in general you dont just process the same data over and over. If you look at the architecture you have coherency problems and bandwidth problems. If you were to analyze many applications, many of the cores would just be idle waiting for data input or output. Also the program(s) running on the cores need to be relatively small. I mean all cores can see what the others are doing, but how do you manage that? Hence the result really expensive super computers ...
Agreed, bandwidth CAN be a killer, but there are plenty of applications that require a massive amount of processing per byte. Here are some of the applications we think the Parallella would be great at:
finger print matching
content based image retrival
optical character recognition
automated optical inspection
number plate recognition
synthetic aperture radar
smart stream compression
large focal array sensor imaging
Complete list here:
The first WANT-NOW app for this beast should ofcourse be a FPGA sim,synthesis and routing tool!
(Does anyone work to do that with CUDA yet?)
Whoever comes first, let me know and I'll throw my money at you! :)
Someone just emailed me to say: "If you consider 16 or 64 cores a SuperComputer then what is this one with 144 that is shipping now? http://www.greenarraychips.com
There is more to this than just core count, like interconnections. Can we make a 4D-HyperCube like we can with the XMOS (decedents of Imos Transputers)? http://www.xmos.com/resources/xkits?category=XK-XMP-64+Development+Board
I replied "I think the main point here is that a lot of today's really compute-intensive tasks require floating point capability -- to the best of my knowledge, products like Green Arrays and XMOS don't support floating-point."
Max, Thank you for the really kind article! Just want to clarify that I really only designed the first chip myself. The last three chips were a complete team effort, with Roman Trogan being in charge of chip design and Oleg Raikhman in charge of verification and programming tools integration. I supported them from time to time, but spent most of my time failing at fundraising, selling, and marketing..
With the right software, we numerical simulations could be a great fit. The challenge right now is that the software infrastructure for parallel programming still needs a lot of work. That's one of the driving reasons for starting this project. Ironically, the challenge of boot strapping ubiquitous parallel programming is a serial process.
Thanks for the explanation, I will try to understand it as a layman of Computer engineeing: are you saying that some commercial simulation tools still can't run on this supercomputer? Such as Ansys, Silvaco...these are popular simulation tools for semicopnductor.Is it possible to make them run in the near future?
This is excelent and a great bang for the buck IMHO. This is whether you are a believer in this kind of multicore approach or not. At the very least you can see the board as a Zync-7000 development board as well, which the cheapest I could find was around 300 bucks (albeit a stronger sibbling of this FPGA, SoC, whatever...). As a (big) bonus you have this nice parallel core (the Epiphany)that you can play with, and who knows what kind of applications can be devised that can make a very good use of it. The sky (imagination) is the limit! :-)
Thank you. Yes, we got lucky with our choice of the Zynq, it has generated an incredible amount of really positive interest.(not even related to the goal of this project:-)) I guess that's what they call "fortuitous serendipity".
This is very interesting.
I myself have just finished developing a 64-processor chip targeted at Ethernet packet inspection and filtering.
The processor cores are optimised hardware implementations of the "Berkeley Packet Filter" processor.
The 64-processor cores are implemented on a Xilinx Virtex-6 FPGA and makes good use of its DSP48E1 primitives and on-chip block-rams to achieve single-cycle operation for most instruction op-codes.
This allows 4x10Gbps of Ethernet packets to be inspected, analysed and filtered at full-line rate on the chip.
This means you can now replace a full rack of servers with a single PCIe card.
Here is the finished product:
This product has applications in:
Network intrusion detection (IDS)
Virus Signature Detection
This is very interesting. I have an assortment of platforms: Arduino Uno, Raspberry Pi, Altium NanoBoard and have just ordered an Arduino Due.
To me this is just as exciting as the January '75 Popular Electronics article introducing the Altair 8800. I ordered one right away and nothings been the same since.
My interests have included machine vision and the platforms I have now, except maybe the NanoBoard, are totally inadequate.
As soon as I figure out how I will cough up the $99 donation.
Big processing power at 5watts power consumption. Initially there will be lot of requirement for the applications in the mobile plate form. Later on desk top systems also.Probably after its launch this will be tuned up further with feed back from the users.
Those who funded will know by now that they met their 750K goal, so I'm looking forward to receiving my dev boards. It's a fascinating project, and it was partly the idea of these guys designing cutting-edge silicon in their basement that encouraged me to put in a few $. As someone said back there, it takes you back to the good old days!
Replay available now: A handful of emerging network technologies are competing to be the preferred wide-area connection for the Internet of Things. All claim lower costs and power use than cellular but none have wide deployment yet. Listen in as proponents of leading contenders make their case to be the metro or national IoT network of the future. Rick Merritt, EE Times Silicon Valley Bureau Chief, moderators this discussion. Join in and ask his guests questions.