Further, in Fig 11 the output stage is not complementary (push-pull) driven as is the case in Fig 12. In fig 11 Q7’s collector is loaded by a standard constant current source formed by Q9. In fig 12, Q10, Q12, form the complementary driver for Q16; there is no such complementary driver for Q9 in Fig 11.
Note also the extra bias current of fig 12, where Q9 is biased at 1mA, Q11 at 6mA, and Q15 at 7mA. Whereas in fig 11 the trans-impedance stage has bias currents of 1mA for Q6, and 6mA for Q7; there is no third stage biased at a current close to that of Q7.
Looking at transistor count: Fig 11 has a total of 11 transistors. Fig 12 has a total of 18; the extra 7 transistors are due to:-
a) folded cascade level shifter (3 extra if we include Q6);
b) one extra gain transistor (Fig 12s Q11)
c) three extra for the complementary driver (Fig 12s Q10, Q12, Q14).
For a fair comparison pitting purely topology against topology, perhaps it would be fairer to throw an extra 7 transistors at Fig 11 (say, by adding an extra gain transistor between Q6 and Q7 biased at about 6mA, and then add a complementary driven load for collector of Q7), and then seeing how they compare.
If that is done, then it may well happen that the amplifier of Fig 12 may still come out ahead for the measurements of interest (THD +N, and power supply ripple rejection); but I suspect the difference may not be all that great.
This is a good topology; it has nice features (like the signal remaining a current right up until being converted to a voltage by a well-biased common-base stage that can charge/discharge capacitances rapidly). However, I’m not so sure the comparison of the “amplifier with new trans-impedance stage” in fig 12 with the “standard 2 stage topology” of figure 11 is entirely fair.
The amplifier of fig 12 has an extra transistor providing gain compared to the amplifier of fig 11. In Fig 12 the current signal output of the differential stage (the folded cascade stage does not amplify, it only provides a level-shifting function) is amplified by TWO transistors: both Q9 and Q11. This amplified current then gets converted to a voltage by the common-base amplifier stage Q15. This is three (3) transistors in total providing the gain of the output signal from the differential stage. Compare this with figure 11. Only Q6 and Q7 (forming a trans-impedance amplifier) amplify the output of the differential stage.
Q9, Q10 with collectors together and to gnd, and bases together: Yes I can see that these just buffer the signal (current) at Q5 collector before reaching Q11 Q12, however I would feel more comfortable it they operated with some voltage across their respective CB junctions - at least the SPICE modelling would be more accurate, I think; plus the Ft should be better (higher), so maybe those feed-forward capacitors C4, C5 could be smaller. A Vbe multiplier (or diode string) between collectors of Q5 and Q8 (with bypass capacitor) would be just fine for this, so that Q9 and Q10 both operate with Vcb of about 2V. This would not affect Q11 and Q12 except for reselecting bias resistors R13, R14.
Also I note there is just one diode string for the bias voltages for the output stage and input stages. This means signal (and load) current modulation of the base currents of Q15, Q16 will affect currents flowing in bias diodes D1 to D10, which will then affect the other stages.
Question: is there a reason the bias voltage for input stage (Q3, and Q4, Q5) is higher that of the output stage Q15, Q16 (5 diode drops vs just 2), or is this an attempt to reduce the aforementioned bias voltage modulation without resorting to separate bias networks and their associated increased bias current?
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.