While this article is focused on the chip creation process, it is equally applicable to the board level creation process, also at the advanced nodes. High density designs in this arena also need electrical awareness from top to bottom. EDA vendors are starting to address this with integrated tool suites incorporating schematic, simulation, PCB and documenation all rolled into one. These tools don't go far enough yet. We routinely work at geometries on the PCB that once were reserved for silicon. We have mixed signal and have to do current density analysis as well as thermal flow analysis. SI analysis is also an integral part of PCB layout and unfortunately, very few DRC tools understand how to check for unbroken return paths, proper termination placement and unexpected radiation. Parasitics from the layout need to be extracted and moved back to the simulation environment to tighten the design so it can be adjusted prior to finalization. Gone are the days when we can just throw a design over the wall to the next step in the process. More and more, the entire vertical process belongs in the hands of a single engineer, and the tools need to support that approach. As no engineer can be expected to know and comprehend all the technologies that may appear on a board,a team is now divided horizontally, so the tools need to permit collaborative efforts. Such tools are just starting to emerge, but not all are on the band wagon. At this time, only a small percentage of project absolutely fall into this category, but as time moves on, these sorts of things will become the norm. Just think of the many tools we have for board and system design that used to be the province of silicon designers. Perhaps its time for that lag to disappear.
Although this piece is so full of "marketspeak" that I needed to translate every sentence to get the drift, the point is an excellent one. Those of us who work in the low-level, wide dynamic-range analog world called "audio" learned long ago that "auto-routing" circuit boards leads most often to disaster. Given the generally poor state of analog skill, an auto-router that embraced common-impedance coupling, magnetic loop areas, and electric field coupling could eliminate thousands of badly-designed products. In audio, most of these bad designs pass bench tests but have horrible problems when connected into real-world systems where power-line noise and significant shield currents exist. I dub many of these "sensitive" designs as "power-line primadonnas".
Replay available now: A handful of emerging network technologies are competing to be the preferred wide-area connection for the Internet of Things. All claim lower costs and power use than cellular but none have wide deployment yet. Listen in as proponents of leading contenders make their case to be the metro or national IoT network of the future. Rick Merritt, EE Times Silicon Valley Bureau Chief, moderators this discussion. Join in and ask his guests questions.