The biggest problem today is heat extraction from inner layers. Once extracted to the surface, heat removal is no different from today's chips. But since the total system dissipation is significantly reduced from the 2D case, the overall system cooling requirements are reduced for the same design.
The physics of heat removal requires your conduction path not to heat up. So power line is not the way. You need something like the a/c where heat is extracted from the conduction path itself, by circulating cooling fluid, most simply air. But the power consumption for cooling must then be taken into account.
Good point @Zeev00, Feyman predicted that long time ago ("there is plenty of room at the bottom". Again using biological analogy: our brain is a 3D device...but we need to reduce power before going 3D, else there is no way to solve heat extraction problem...reducing computational accuracy, or moving to analog computing (as the brain does) would be useful to accomplish that...Kris
The only path to systematically reduce power seems to be to go 3D. I am not talking about the TSV 3D path, but the monolithic 3D one. With monolithic 3D integration the interconnects are shorter, and hence their capacitance and power; the off-chip drivers and their large power are gone; and heterogeneous integration saves yet another high-power chip-crossing signalling.
"Approximate data can reduce the computing load significantly. We have to start looking at the way we do computing from a system point of view." - I think is the key takeaway from that talk...our computing is too exact, we calculate everything with 32 or 64 bit accuracy...no need...look at our brains, work much better (pattern recognition for example) despite being much slower
Blog Doing Math in FPGAs Tom Burke 13 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...