MRAM is a proven solution for protection of data in the event of system power loss because it is inherently non-volatile, there is no additional time needed to write data to a secondary non-volatile array, it simplifies the controller design, offers the speed of RAM and has superior endurance. MRAM is processed using standard CMOS base wafers to provide low cost as well as lower overall TCO to the user. Everspin, the leader in MRAM technology,announced customer sampling of the world's first commercial Spin Torque MRAM in a 64Mb density with a DDR3 interface. Now in one device the user can have power fail safety, non-volatility, DRAM DDR3 compatibility, with ultra low latency. With MRAM users can choose between SRAM like interface with existing products in volume production as well as look to the future with ST-MRAM in DRAM like interfaces.
Neale, 16Mb is planned for first quarter of 2013, with 32Mb in fourth quarter.
16Mb devices are on 130nm node.
Based on the future requirements and feedback from customers, the density requirement would be in the range of 32Mb - 128Mb.
We have not evaluated PCM as a major competitor. I will check on PCM and get back to you.
nvSRAM is completely on the standard CMOS manufacturing process and this is a big advantage in terms of both cost, manufacturability and supplier reliability. MRAM, on the other hand is on a non-standard process, which translates to higher costs.
SSD write cache density would be in 100s of MBs to GBs range, but only a portion of that data (metadata) needs to be backed-up reliably on power loss and that is where nvSRAM solution comes in. Replacing all of the SDRAM write cache with nvSRAM would be the ideal solution. But, those densities are currently out of reach.
Pramodh a couple of questions. What is the timeline for bit capacity greater than the 16-Mbit planned for production in the first quarter of 2013. What is the lithographic node for the 16-Mbit you (Cypress) are now sampling?
Looking at the future requirements of enterprise SSDs enterprise servers, what in your view is likely to be the bit capacity requirement for SRAM or your nvSRAM?
What is your view of PCM as a competitor for this SSD role?
How does an nvSRAM compare with the new MRAM technology in terms of cost and reliability? It seems that MRAM is ultimately a better solution, since it is non volatile, does not require a data transfer, and does not require a back-up power source. MRAM also has SRAM-like interfaces and timing...
Clearly, nvSRAM has an advantage in terms of density, but how much is actually required for a an SSD write cache?
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.