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AnneM_#1
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re: Startup CogniMem demos new road to computing
AnneM_#1   11/15/2012 9:55:15 PM
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Actually, the innovation is that the N CM1K chips residing on a stack (4 per stackable board) make a bank of N*4096 cognitive memories responding in parallel to an input pattern (like a massive lookup with parallel access). The RBF and KNN classifiers are inherent to the bank of CM1Ks.The FPGA is used to configure the CM1Ks into a single or multiple banks, handle comm with hosts,etc. With regards to your question, CogniMem web site has an RBF Tutorial for download as well as a ref guide.

anon5532556
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re: Startup CogniMem demos new road to computing
anon5532556   11/14/2012 6:31:25 PM
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It does indeed. Transputers had limitations but not nearly that of old school stuff. Like a lot of things they did incredible stuff with the right people driving them, but were anathema to most people. It was sad to watch them kicked to the side by the main streamers.

PanPilot
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re: Startup CogniMem demos new road to computing
PanPilot   11/14/2012 4:41:32 PM
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In some ways, this sounds like a modern take on the 'Transputer' devices of the 80's. Huge claims were made at the time, I recall; the Transputer was going to revolutionise everything...

alainsan
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re: Startup CogniMem demos new road to computing
alainsan   11/13/2012 10:54:48 PM
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it seems that the innovation would be in the algorithm. The hardware looks very similar to other fpga clusters like sciengines, or dini group or comblock modules. Can anyone point to a good tutorial paper on "non-linear classifiers Radial Basis Functions and K-Nearest Neighbor" or patent maybe?

ZISC1
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re: Startup CogniMem demos new road to computing
ZISC1   11/13/2012 4:38:47 PM
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Each neuron is a 256 bytes SRAM. MRAM access time (R/W) is 35 ns... The CBX MRAM is use mostly to keep the "knowledge" aka Cognigram during powerdown conditions.

ttt3
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re: Startup CogniMem demos new road to computing
ttt3   11/13/2012 4:35:40 PM
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Sounds like they need non-volatile SRAM, which MRAM (and FRAM) emulates nicely. Per Everspin's website: "Parallel MRAMs (8-bit and 16-bit) have SRAM read and write cycle times and asynchronous timing interfaces that use standard SRAM access timing."

resistion
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re: Startup CogniMem demos new road to computing
resistion   11/13/2012 3:33:45 PM
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If they wanted response speed, why not SRAM instead of MRAM.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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