Actually, the innovation is that the N CM1K chips residing on a stack (4 per stackable board) make a bank of N*4096 cognitive memories responding in parallel to an input pattern (like a massive lookup with parallel access). The RBF and KNN classifiers are inherent to the bank of CM1Ks.The FPGA is used to configure the CM1Ks into a single or multiple banks, handle comm with hosts,etc. With regards to your question, CogniMem web site has an RBF Tutorial for download as well as a ref guide.
It does indeed. Transputers had limitations but not nearly that of old school stuff. Like a lot of things they did incredible stuff with the right people driving them, but were anathema to most people. It was sad to watch them kicked to the side by the main streamers.
it seems that the innovation would be in the algorithm. The hardware looks very similar to other fpga clusters like sciengines, or dini group or comblock modules. Can anyone point to a good tutorial paper on "non-linear classifiers Radial Basis Functions and K-Nearest Neighbor" or patent maybe?
Sounds like they need non-volatile SRAM, which MRAM (and FRAM) emulates nicely. Per Everspin's website: "Parallel MRAMs (8-bit and 16-bit) have SRAM read and write cycle times and asynchronous timing interfaces that use standard SRAM access timing."
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.