Actually, the innovation is that the N CM1K chips residing on a stack (4 per stackable board) make a bank of N*4096 cognitive memories responding in parallel to an input pattern (like a massive lookup with parallel access). The RBF and KNN classifiers are inherent to the bank of CM1Ks.The FPGA is used to configure the CM1Ks into a single or multiple banks, handle comm with hosts,etc. With regards to your question, CogniMem web site has an RBF Tutorial for download as well as a ref guide.
It does indeed. Transputers had limitations but not nearly that of old school stuff. Like a lot of things they did incredible stuff with the right people driving them, but were anathema to most people. It was sad to watch them kicked to the side by the main streamers.
it seems that the innovation would be in the algorithm. The hardware looks very similar to other fpga clusters like sciengines, or dini group or comblock modules. Can anyone point to a good tutorial paper on "non-linear classifiers Radial Basis Functions and K-Nearest Neighbor" or patent maybe?
Sounds like they need non-volatile SRAM, which MRAM (and FRAM) emulates nicely. Per Everspin's website: "Parallel MRAMs (8-bit and 16-bit) have SRAM read and write cycle times and asynchronous timing interfaces that use standard SRAM access timing."
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.