When you have a resistance-based memory like PCM or STT MRAM and it needs to scale to lower currents, there don't seem to be any chip array testers (not individual cell probes) that can go down to nano amps for read currents. Hope this situation will change.
Peter did you mean this ""Much like other types of NVM technologies, a PCM cell must be formed before it displays the consistent switching necessary to be a memory element.""
While PCM has a number of problems, the need to “form” the device should no longer be necessary. Imagine the problems, cost and time, of forming each bit of an 8G-bit array. Unless the author knows something that we are not being told forming effects should have gone away with the use of the crystallized active material as one electrode in the PCM structure.
In the distant past, when PCM devices were fabricated with the active material in the amorphous state then there is a first switching (or forming) pulse. This is because the state of disorder, which determines the threshold voltage, of the as deposited film, differs from that of the same material after the first set/reset cycle, also there may have been some element separation that may have an impact on the value of the threshold voltage. While it is still necessary to empirically establish the optimum operating parameters by an iterative process for each new PCM device structure I think the author may have inadvertently confused that process with a need for forming. Once the optimum operating conditions are established with crystallized active electrodes there should be no need for forming.
One other question have the annotations for Current and Voltage been accidentally transposed in Figure 7 or is this a power PCM device??